KB: DIO state when nRESET PIN is LOW

Question

What is the DIO state when the nRESET PIN is LOW ?

Answer

In the reset state while the nRESET pad is driven low, the DIO output drive is disabled and a weak (250 kΩ) pull-down resistor is enabled.

After reset is released, the default DIO configuration is applied (based on the core voltage 1.2V is stable condition.)

NOTE:

Be careful, as all the DIOs will now have a 250 kΩ terminal load if another chip is connected with RSL10 DIOs while nRESET is LOW.

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