# Question

Programming an audio app requires setting the sample frequency with RSL10. How is this sample frequency obtained?

# Recommendation

For example, to find the sample rate of DIMC, see the example below:

We set RF_clk = 48M/6 = 8M

And let SYS_clk  = RF_clk

Then set audio_clk = 8M/4 = 2M

Set DMIC_clk = audio_clk

Final set sample rate = 2M/64 = 32k

You can use a similar method to get the OD output sample rate; it should work out to 16k.

I have a few questions to confirm whether I understood this correctly or not.

1. Here the final DMIC sampling rate turns out to be 2M/64 = 31,250 Hz and not exactly 32k. Is this correct?

2. Similarly, assuming the sampling frequency for OD is half of this value, it is actually 15,625 Hz and not exactly 16k. Is this correct?

3. I don’t see where exactly the frequency for OD has been set. I understand that SYS_clk = RF_clk = 48/6 = 8 MHz, and using AUDIOCLK_PRESCALE_4 and AUDIOSLOWCLK_PRESCALE_2 will cause the AUDIOSLOWCLK value to be 8/4/2 = 1 MHz. From the first parameter of AUDIO_CONFIG I can also see that the OD clock source has been set to AUDIOSLOWCLOCK (which I understand to be 1 MHz at this point). Is the DECIMATE_BY_64 also supposed to divide OD clock by 64 here? In RSL10_hardware_reference.pdf, page 379 section 13.1.1.1 says something about OD interpolation rate.

So this means OD clock source and DMIC clock source are both divided by the DECIMATE_BY_64 parameter when calling the Sys_Audio_Set_Config(AUDIO_CONFIG); function. Is this correct?

4. I would like to get an exact sampling frequency of 16 kHz in both DMIC and OD. I am planning to configure audio using the following parameters:

/* Enable 48 MHz oscillator divider to generate a 16 MHz clock. */
RF_REG2F->CK_DIV_1_6_CK_DIV_1_6_BYTE = CK_DIV_1_6_PRESCALE_3_BYTE;

/* Wait until 48 MHz oscillator is started */
while (RF_REG39->ANALOG_INFO_CLK_DIG_READY_ALIAS !=
ANALOG_INFO_CLK_DIG_READY_BITBAND);

/* Switch to (divided 48 MHz) oscillator clock */
Sys_Clocks_SystemClkConfig(JTCK_PRESCALE_1 |
EXTCLK_PRESCALE_1 |
SYSCLK_CLKSRC_RFCLK);

/* Configure AUDIOCLK to 3.2MHz, AUDIOSLOWCLK to 1.6 */
Sys_Clocks_SystemClkPrescale1(AUDIOCLK_PRESCALE_5 | AUDIOCLK_PRESCALE_2);

In app.h, I plan to define the following configuration settings:

#define DECIMATE_BY_200                 ((uint32_t)(0x11U << \
AUDIO_CFG_DEC_RATE_Pos))

/* Audio configurarion for OD */
#define AUDIO_CONFIG                    (OD_AUDIOSLOWCLK                        | \
DMIC_AUDIOCLK         | \
DECIMATE_BY_200                    | \
OD_UNDERRUN_PROTECT_ENABLE | \
OD_DATA_MSB_ALIGNED        | \
DMIC0_DATA_MSB_ALIGNED     | \
DMIC1_DATA_MSB_ALIGNED     | \
OD_DMA_REQ_DISABLE         | \
DMIC0_DMA_REQ_DISABLE      | \
DMIC1_DMA_REQ_DISABLE      | \
OD_INT_GEN_DISABLE         | \
DMIC0_INT_GEN_ENABLE       | \
OD_ENABLE                  | \
DMIC0_ENABLE )

This is a combination of the settings used in DMIC_OD and the OD_SINE_TEST sample given here: KB: Suggested Settings and Register Definitions for the RSL10 Output Driver (OD)

I am assuming that this setting will give me exactly 16 kHz sampling frequency for both DMIC and OD. Is this correct and is there a way to confirm it?

1. Can you please explain how to determine timer period, in an easy to understand way as you have done here for the DMIC and OD sample frequency? I need to understand the timer_free_run sample program (and it’s difference from timer_driver sample program, if possible). For reference my previous question about it is here, How do I calculate the period of a general purpose timer in rsl10?

Hi, @mahaju you’re right in original setting of DIMC_OD sample, the sample rate should be 15.625kHz

if you want to get the sample rate, you could set a test DIO as below in DMIC_OUT_OD_IN_IRQHandler