How to check for "Power on Reset" POR using DIG & ACS RESET_STATUS?

Sample code sleep_RAM_retention/main.c checks reset source as

    /* Check reset source to see if wake-up from sleep */
    if ((DIG->RESET_STATUS == 0x1) && (ACS->RESET_STATUS == 0x0))
    {
     ...
    }
    else
    {
        /* Power-on reset */
     ...

According to the hardware reference,
DIG_RESET_STATUS = 0x1 means “ACS RESET was triggered”,
A) is it possible for ACS_RESET_STATUS to be 0x0?

and a Power-on Reset is detected ONLY if bit field 8 of ACS_RESET_STATUS is set to 1.
B) If this is the case, why checking for the rest of cases (i.e. “else”)?

A wakeup from sleep condition is indicated by the ACS_RESET_FLAG bit in the DIG_RESET_STATUS register being set and the absence of any other digital or asynchronous reset. Therefore the test to enter the “if” body evaluates all the DIG_RESET_STATUS and ACS_RESET_STATUS bits. The “else” body is entered if the cause of waking was any type of reset event and not a wake from sleep.

To address question A - the ACS_RESET_STATUS bit value is shown by the hardware reference manual as unknown so possibly zero in the case of software or watchdog timer resets. Please note that the code here isn’t testing so much that ACS_RESET_STATUS is not zero, but instead that it is the only bit set.

Thank you for using the community forum.

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Please address every point in the following:

  1. Do I understand correctly, DIG_RESET_STATUS = 0x1 and ACS_RESET_STATUS = 0x0 (say condition A) means a “wakeup from sleep” was triggered at least once since the status was last cleared?
  2. if condition A is not true, does that mean a “Power-on reset” was triggered … as stated but the comment?
  1. Correct
  2. The comment is potentially misleading. If condition A is not true then some other reset occurred and the program is behaving as if a power on reset occurred. The DIG_RESET_STATUS And ACS_RESET_STATUS bits could be further decoded to determine the actual cause of the reset.

In our firmware we see more than one bit set, i.e. the following values for
(DIG_RESET_STATUS, ACS_RESET_STATUS) =
Case A) (0x1, 0x7F00)
Case B) (0x1, 0x4200)

How would you decode/interpret this values?

Following Figure 5 in the Hardware Reference Manual:
Case A)
DIG_RESET_STATUS=0x01 => Asynchronous Reset occurred, so we look at the ACS_RESET_STATUS. In ACS_RESET_STATUS, POR_RESET_FLAG is set, so ignore all the other bits and we see a “Reset due to PMU-POR” has occurred since the reset flags were last reset.

Case B)
DIG_RESET_STATUS=0x01 => Asynchronous Reset occurred, so we look at the ACS_RESET_STATUS. In ACS_RESET_STATUS, POR_RESET_STATUS is clear and PAD_RESET_FLAG is set. Per the table in this condition the other status bits should be ignored and this is a “Reset due to the NRESET pad” condition.

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Thank you for your feedback.

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