FAQ: PLL lock issue

Q: We measured the time it takes for the PLL to lock during transmission. Although the spec says that it is between 5us and 50us, we have observed up to 375us lock time. Furthermore, when a packet is received just before one is transmitted, it sometimes (though not often) unlocks the PLL after previously being locked. It seems that the state of the radio prior to transmitting is very important. For instance, if we follow the user manual transmitter flowchart (figure 9), we should first go to FULL_TX and then push the data in the FIFO. When doing that, it often happens that the PLL does not lock at all (even after 10ms!). However, if we start with XTAL on, then turn on the FIFO, then TXSYN, and finally TX; then the PLL will lock almost every time. It does not always lock though if a reception has happened just before. How can we fine tune the PLL locking algorithm to reach a reliable 5us to 50us lock time? Is there a tech note on that?

A: The PWRMODE register should not be changed directly from FULL_RX to FULL_TX, see the following erratum sheet at: https://www.onsemi.com/pub/Collateral/AX5043-ERR-D.PDF
Otherwise the FIFO may end up in an undefined state, which can prevent the PLL from locking.
To get faster locks try increasing the PLLCPI register from 0x01/0x02 to 0x08. The low CPI setting reduces the PLL bandwidth and thus may lead to longer lock times. For more details on the registers check out the programmers manual.