The AX5043 supports hardware Forward Error Correction (FEC) that transparently adds redudancy to the transmit data to make it more immune against noise.
FEC encoding can only be used together with High-Level Data Link Control (HDLC) flags (0x7E) as preamble characters. The HDLC framing is shown in the Table below (taken from AX5043 Datasheet ):
In HDLC mode, frames start and end with the bit pattern 01111110 (0x7E). Such framing is automatically added to the user packet. Additionally, in order to ensure that no bit pattern inside the frame can be erroneously detected as a frame end, the transmitter inserts a 0 bit after five consecutive 1 bits; the receiver automatically removes those inserted 0 bits, making the process transparent to the user. At the end of an HDLC frame, a checksum is transmitted. Seven or more consecutive one bits are treated as an ABORT, causing the current packet to be discarded.
When FEC is enabled, two new blocks are inserted into the transmit chain between encoder and modulator:
- An encoder adds redundant bits to the bitstream;
- An interleaver reorders the bitstream.
The inverse operations are inserted into the receive chain:
- A deinterleaver and its associated synchronization circuitry re−reorders the bits into their natural order;
- A Viterbi decoder recovers the original transmit bits.
FEC can be enabled directly in AX-RadioLab, by selecting the FEC encoding in the PHY Panel. HDLC framing will be automatically set in the Framing Panel.
More information on the FEC engine can be found in this app note written for the AX5042, but also valid for the AX5043: https://www.onsemi.com/pub/Collateral/AND9309-D.PDF