FAQ: How to operate AX5043 at 27 MHz - (custom matching networks for AX5043)


What is the procedure for operating AX5043 at 27 MHz?


27 MHz is at the low end of the frequency range that AX5043 was designed for. Because applications are seldom built for this low range, ON Semiconductor has not provided a formal reference design. However, some work has been done to configure the AX5043 at this frequency. This post summarizes what work has been done, and the limitations of operating at this frequency.

The first important note to make is that, as can be seen in the chart below (which is included in the AX5043 datasheet), lower frequencies require larger external tuning inductors for the internal VCO. Additionally, the gain of the VCO (K_VCO) decreases dramatically as the inductance size increases. This means that the PLL has a much smaller range of available frequencies to lock to for a given inductor value. One issue we’ve seen is that unless extremely tight tolerances are used on this tuning inductor, a test bench design at 27 MHz may experience issues in production. This is because the slight variations in inductance place the entire PLL tuning range outside of the desired RF operating frequency band.

To verify operation at 27 MHz, the reference design on the 169 MHz evaluation kit was modified and a transmit test was performed. Detailed below are the steps taken to make the modifications, so that they can be replicated for other frequencies.

Class E Amplifier Load network

For some theoretical background of class E amplifiers the following paper is an excellent introduction:

In this next paper, the authors defined a system of equations that can solved to quickly determine component values that satisfy class E operation.

The equations given in this article were used to calculate the following values for the class E load network:

  • LC1/2 = 680 nH
  • CC1/2 = 120 pF
  • CT1/2 = 120 pF
  • LT1/2 = 470 nH

For the Balun components, an online calculator was used to generate the following values:

  • LB1/2 = 390 nH
  • CB1/2 = 82 pF

The Harmonic Filter was designed with the online tool here:

  • CF2/3 = 180 pF
  • CF1 = 43 pF

PLL External Inductor

The inductor was chosen based on the datasheet equations, with some manual fine-tuning. PLL Lock was acheived with using a parallel L/C combination as a tuning impedance (LVCO) for the internal VCO:

  • C = 5.6 pF
  • L = 820 nH


Testing and Results

This design was tested on the DVK-2 Platform, using code generated with AX-RadioLab. Using the TX CW test mode firmware, configured by AX-RadioLab to operate at 27 MHz, a clean signal at over 13 dBm was measured, after accounting for cable loss:


Harmonics were also suppressed with the filter:

The output was also able to be successfully modulated:


I use v2.8e AX-RadioLab to input 27Mhz in Carrier Frequency and press Enter, Carrier Frequency automatically restores to 70Mhz. How can I deal with this problem?

RadioLab tries to help customers avoid modes that may require extra testing and debug work including this situation.

If you type ‘1962’ in the Tx periodic window where the time parameter goes it will unlock RadioLab and allow you to make this change.

Thank you for asking and let us know if this doesn’t work for you.

Thank you for using the community forum!

I have purchased the DVK-2 and 169 MHz evaluation kit and downloaded the AX-RadioLAB application. Is there any recommended setting parameters for the four items of Kit Configuration, Pin Configuration, PHY and Framing to complete the test (27Mhz)

Hi Justin, if you don`t have any specific protocol to implement a part from the frequency at 27 MHz, let RadioLab do the calculations for you and just change the following:

  • Kit configuration: leave the default options (device: AX8052F100 and Kit Type: AX8052 DVK-2).
  • Pin Configuration: leave default values, set only VCO Config to “VCO 2 (external inductor)”
  • PHY: you can copy what is displayed in the thread above (double check to set the correct TCXO frequency).
  • Framing: you can leave the default values.
    Thank you!

With class E amplifier, how do I understand the use of LC1 & CC1, LC2 & CC2, LT1 & CT1, LT2 & CT2.
I tried to use the equation given in the article “Load Network Design Techniques for Class E RF and Microwave Amplifiers” to calculate the value of the Class E load network, but I could not calculate the 27MHz LC1 & CC1, LC2 & CC2, LT1 & CT1, LT2 & CT2 Value, how do I understand
Does AX5043 provide S parameter? How do I get it

Maybe this will help you identify which components are part of the class E network.

As far as s-parameters, please refer to this post: FAQ: Output impedance on the AX5043 ANT pins

I understand that LC, CC, CT, and LT constitute a class-e amplifier network. CT and LT are resonant circuit , but are LC and CC RF chokes? Why is the other end grounded?

The LC inductors are indeed RF chokes, and they are grounded because the power amplifier uses p-channel transistors which require a DC path to ground for biasing.

Many other chips use n-channel transistors and in that case the circuit is flipped.

The CC capacitors are part of the class E operation as you can see in the papers linked to above.

Hi, I have a custom board that is supposed to operate at 27 MHz. I have already got a communication working at 868.3 MHz and have now adapted the circuit for 27 MHz. My problem is that the PLL no longer locks in the lower frequency range. With an external inductor of 440nH (2x 220nH) I still get a lock at about 30 MHz. But if I increase the inductor to 680nH, the PLL locks at about 50.6 MHz.
I always look for a lock by setting the FREQA register to 25000000, performing auto-ranging and increasing the contents of FREQA by 100 and repeating this until autoranging is successful.
My question is:

  • What kind of inductor do I need to use as an external inductor for the VCO? The data sheet does not say anything about this.
  • Why does AX-RadioLAB set REFDIV to 1 in register PLLVCODIV? What does this parameter mean?
  • What is the internal oscillating circuit of the VCO like?
  • Is there anything else I have to consider or can try out?

Hello @psche, thanks for using the forum!

We don’t have a lot of experience with 27 MHz operation but earlier in this thread my colleague shared he was able to get a lock at 27 MHz using an external inductor of 820 nH and a parallel cap of 5.6 pF.

It will be different on your board. We know that the VCO gain at low frequencies is not very big so you have to be fairly precise with the inductor value. You may need to put two inductors in series to get you closer to the ideal value for your board.

The inductor should be as high of a Q as you can find and as precise as you can get it so you can minimize spread in the center frequency from board to board.

The applications team does not have knowledge of the exact circuit of the VCO in ax5043.

REFDIV is a divider that scales the frequency in the PLL feeding into the phase detector. See the ax5043 programming manual for details. Here is what is inside the document for REFDIV:

2 posts were split to a new topic: How to use ‘printf’ on DVK-BASE-2+ADD5043 and AX8052F143

2 posts were merged into an existing topic: How to use ‘printf’ on DVK-BASE-2+ADD5043 and AX8052F143

Hi @justin.h725, how is the external inductor (820nH parallel with 5.6pF) for VCO working in your design? In my case, the PLL is hard to lock at 27MHz. any specific point I shall be aware of? THX

I’m trying to use AX5246 on 144MHz band.

there is linked article: “Load-Network-Design-Techniques-for-Class-E-RF-and-Microwave-Amplifier.pdf”

On page 25, there is equation:

R=1.365*Vcc^2/Pout in which as I understand Vcc=VDD_ANA

What values of VDD_ANA/Pout I should put into calculations?
I would be also satisfied by ready values of matching network.

Hello. In the formula you should use 1.8V as VDD_ANA, and Pout as the power that you are targeting (40 mW?).
For 144 MHz you could start from the 169 MHz network ADD5043-169-2-gevk schematic.pdf and slightly adapt the components to the lower frequency (and of course also choose a different Lext inductor).

I think I have sorted out how to calculate LC1/CC1, however I am a bit confused by LT1/CT1 values shown here and in the example matching networks. From reading the papers linked above, it seems that LT1/CT1 should be resonant at the frequency of operation, ie. they should satisfy f0 = 1/(2π sqrt(LC)).

However, if I evaluate this for the values given above, the resonance is only ~21MHz, and similarly the 169MHz example network resonates at ~145MHz. Is the discrepancy to account for some parasitics etc., or am I missing something fundamental?

Hi psche. Were you able to get this worked out? If so, can you provide details? We are in the same position and are trying to work toward a solution. Thanks

Hi @keenan.tims, your understanding and calculations are correct. The equations in the paper are used as very good starting point, but some fine tuning is then always necessary at board level. Note also that there are constrains on the actual values of L&C limited to the available series (e.g. E12, E24, etc. ) so one could not always match the exactly right values that the equations give.