What is the procedure for operating AX5043 at 27 MHz?
27 MHz is at the low end of the frequency range that AX5043 was designed for. Because applications are seldom built for this low range, ON Semiconductor has not provided a formal reference design. However, some work has been done to configure the AX5043 at this frequency. This post summarizes what work has been done, and the limitations of operating at this frequency.
The first important note to make is that, as can be seen in the chart below (which is included in the AX5043 datasheet), lower frequencies require larger external tuning inductors for the internal VCO. Additionally, the gain of the VCO (K_VCO) decreases dramatically as the inductance size increases. This means that the PLL has a much smaller range of available frequencies to lock to for a given inductor value. One issue we’ve seen is that unless extremely tight tolerances are used on this tuning inductor, a test bench design at 27 MHz may experience issues in production. This is because the slight variations in inductance place the entire PLL tuning range outside of the desired RF operating frequency band.
To verify operation at 27 MHz, the reference design on the 169 MHz evaluation kit was modified and a transmit test was performed. Detailed below are the steps taken to make the modifications, so that they can be replicated for other frequencies.
For some theoretical background of class E amplifiers the following paper is an excellent introduction:
In this next paper, the authors defined a system of equations that can solved to quickly determine component values that satisfy class E operation.
The equations given in this article were used to calculate the following values for the class E load network:
- LC1/2 = 680 nH
- CC1/2 = 120 pF
- CT1/2 = 120 pF
- LT1/2 = 470 nH
For the Balun components, an online calculator was used to generate the following values:
- LB1/2 = 390 nH
- CB1/2 = 82 pF
The Harmonic Filter was designed with the online tool here:
- CF2/3 = 180 pF
- CF1 = 43 pF
The inductor was chosen based on the datasheet equations, with some manual fine-tuning. PLL Lock was acheived with using a parallel L/C combination as a tuning impedance (LVCO) for the internal VCO:
- C = 5.6 pF
- L = 820 nH
This design was tested on the DVK-2 Platform, using code generated with AX-RadioLab. Using the TX CW test mode firmware, configured by AX-RadioLab to operate at 27 MHz, a clean signal at over 13 dBm was measured, after accounting for cable loss:
Harmonics were also suppressed with the filter:
The output was also able to be successfully modulated: