BLE sleep mode and deep sleep mode difference

Hi I am trying to understand how deep sleep mode and ble sleep mode are different and what steps need to be followed to go into ble deep sleep alone? What configurations must be taken care of for doing this?

@rodeb
Please refer to our knowledge base thread at:

Blockquote KB: Outline of the RSL10 Power Modes

Entering Sleep Mode by writing the sleep key in the ACS_PWR_MODES_CTRL register starts the following sequence:

  1. The system clock is stopped.
  2. Reset is asserted unless the VDDC retention regulator is enabled.
  3. All memories (flash, PROM, RAM) are isolated from the core (AND gates).
  4. Memories are powered off. RAMs which are enabled in the memory enable retention latches are put into
    Retention Mode, if the VDDM retention regulator is enabled.
  5. The logic is disconnected from its supply unless the VDDC retention regulator is enabled.
  6. The baseband timer is disconnected from its supply unless the VDDT retention regulator is enabled.
    RSL10 Hardware Reference
    www.onsemi.com
    56
  7. The RF block is disconnected from its supplies (VDDRF and VDDPA). Note that the RF block needs to be
    isolated manually if the VDDC retention regulator is enabled.
  8. The VDDA, VDDC, VDDM, VDDRF and VDDPA regulators are disabled.
  9. The VCC regulator/DC-DC converter is disabled.
  10. The bandgap is disabled.

Recommendation

For more information regarding the RSL10’s Power Modes, and the Wake-Up sources that can be used to interface with the sleeping device, please read Section 5.4 “Power Modes” in our RSL10 Hardware Reference, available in the RSL10 Documentation Package .

if you use our CMSIS example sleep_RAM_retention you can get low current consumption in sleep mode.

image

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Thanks for the information!

I am further confused about particularly ble shutdown using sleep_RAM_retention code,so for that BLE_Power_Mode_Enter() plays what purpose?
I read in a thread in the forum that deep sleep by default will shutdown the entire BLE and BB hardware,then what ble configurations will be required?

I am trying to understand the ble lld configurations(BLE_LLD_Sleep_Params_Set) done in peripheral_server_sleep sample code, can you please provide some information on these configurations , what for these configurations are required?

In the peripheral_server_sleep code example, between advertising interval and connection interval, chip goes into sleep mode.
This sleep mode is wakeup from RAM. The sleep period current could be **uA.

We have another sleep_ram_retention sample. This is deep sleep mode. It can close all except analog registers. This deep sleep mode is wakeup from flash.

The deep sleep mode (wakeup from flash) could not store any BLE configurations.

image

The normal sleep mode (wakeup from RAM) could store BLE configurations.

The deep sleep mode can have very low current consumption. (**nA).
The normal sleep mode can have higher current consumption. (**uA)

The deep sleep mode have long wakeup time.
The normal sleep mode have short wakeup time.

We could mix these two modes.
For example,

  1. advertising mode for long sleep period or long advertising interval, we could apply deep sleep mode.
  2. connection mode, we could use normal sleep mode.(peripheral_server_sleep)

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thanks, my issue has been fixed.

thanks my issue has been fixed.