AX5043 & STM32 Res

good afternoon, help me set up the registers to accept the format packet (AAAAAAAAAA 91D3 00 01 02 03 04 05 06 07 08 09). This packet turned out to be successfully transmitted from AX5043, and successfully received by transceivers of another manufacturer (RFM66, CC 1120), but to receive the packet on AX5043 does not work out in any way. To begin with, I want at least without coding in its raw form, then I think I’ll figure it out myself. I want to receive using packet ready interrupts in FIFO. The radio parameters used are THDATARATE = 19200 b / s. DEV = 6400Hz. MOD = MSK. I plan on these chips (AX5043) mass production> 100,000 per month. I also plan to test this chip on modulation, I hope to get a better range than in the CC1120 and RFM66. It depends on your help whether we will use this chip at home or not.
My name is Alexander, I am a developer at Ajax Systems.
Below is the code with the help of which a successful packet transfer is made.

void Send_packet(uint8_t *buf, uint8_t len)

	// ********** Preamble  **********
	spi_write(AX5043_REG_FIFODATA,5);  //Preamble_len
	// ********** end Preamble  **********

	// **********  Sync  **********
	spi_write(AX5043_REG_FIFODATA, (AX5043_FIFOCMD_LEN_VAR | AX5043_FIFOCMD_DATA));   
	spi_write(AX5043_REG_FIFODATA, 3);  
	spi_write(AX5043_REG_FIFODATA, 0x38);
	spi_write(AX5043_REG_FIFODATA, 0x91);
	spi_write(AX5043_REG_FIFODATA, 0xD3);
	// **********  Sync  **********

	// **********  Data  **********
	spi_write(AX5043_REG_FIFODATA, (AX5043_FIFOCMD_LEN_VAR | AX5043_FIFOCMD_DATA));  
	spi_write(AX5043_REG_FIFODATA, len + 1);  
	spi_write(AX5043_REG_FIFODATA, Flags);

			spi_write(AX5043_REG_FIFODATA, *buf++);
			len --;

	// ********** end Data  **********
    spi_write(AX5043_REG_PWRMODE, AX5043_PWRSTATE_FULL_TX);

	spi_write(AX5043_REG_FIFOSTAT, 4); // FIFO commit

	fTx_Ready = 0;

	while (fTx_Ready == 0);


Hi Alexander,
I assume you have purchased our full DVK comprised of DVK-BASE-2 + ADD5043. In this case you can quickly evaluate the full MASTER → SLAVE radiolink generating the project using our GUI tool AX-RadioLab.
A guide on how to use the GUI is available at .

For your specific application, you can:

  • in the PHY Configuration panel, insert the details for your physical layer ( THDATARATE = 19200 b / s. DEV = 6400Hz. MOD = MSK). (Note that MSK does not appear by default in the modulation drop down menu. To enable that in the GUI, insert ‘1962’ in the period field as shown below)
  • in the Frame Configuration panel you can use the built in “Raw, Pattern Match” framing mode to achieve the packet format you need. Set a PREAMBLE of 80 bits 0xAA, a 16 bit SYNCWORD of 0x91D3, disable the ‘len byte’ and ‘address matching’, insert your packet in DATA, and disable CRC.

AX-RadioLab will then generate two projects, one for the MASTER and one for the SLAVE, initializing each with the optimal registers settings. Finally, you will be able to flash both MASTER and SLAVE directly via the GUI and get your demo running, and/or open the source code in AX-CodeBlocks to analyze our radio driver and port it to your 3rd party MCU.

Regarding the range, our AX5043 has excellent selectivity that allows reaching market leading radio-link budgets. If even more range is needed, check out our AX5045: Ultra-Low Power Narrow-Band Sub GHz (60 - 1050 MHz) RF Transceiver with Integrated +23 dBm High Power Amplifier

Нет. Я не использую полнофункциональный DVK, а только ADD5043. и я его подключил к STM32.
Но Вас понял, будем покупать полный набор и что-то попытаться настроить. И потом копировать в свой проект.

Hi Alexander, someone from our sales will contact you soon and advice what best DVK you should use.
In the meantime, please find attached a RadioLab generated project with your settings. You can also open the project yourself in Ax-RadioLab (download it from here Software: AX5043).

Note that the AX5043 implements an MSK with h=0 therefore at 19.2kbps you will have a ±4.8kHz deviation. In the Frame Configuration I have added a CRC check to exclude false packets. Also with this project I am experiencing a 30% PER (at RSSI -85 dBm). The performance can be better by increasing the preamble and play with the RX BW. (2.3 MB)

Подскажите пожалуйста в документе
VCO Current Calibration for Optimal Synthesizer Phase Noise
есть запись что калибровку VCO необходимо производить при каждом изменении несущей частоты.
Вопрос: сколько нужно на это времени? так как мне нужно для минимального потребления переключится на 3-х частотах (868.5MHz, 872.5MHz, 880.2MHz) за 3 мс BR = 19200. Это возможно для чипа AX5043?

Can you please tell me in the document there is a note that VCO calibration should be done every time the carrier frequency is changed.
Question: how much time do I need for this? Because I need 3 frequencies (868.5MHz, 872.5MHz, 880.2MHz) to switch in 3ms BR = 19200 for minimal consumption. Is it possible for AX5043 chip?

Hello. The VCO calibration routine cited in the app note is not required for the radio operation. Its purpose is to optimize the phase noise generated by the PLL, by optimizing the VCO current (VCOI). As cited in the note, this calibration requires an external network connecting the radio`s ADC to the FILT pin, and should be done every time the temperature or VDD varies considerably, and when the carrier frequency is largely changed.
What must be done every time there is a frequency change is the PLL auto-ranging in order to lock the PLL onto a new frequency. For this purpose the AX5043 has two frequency registers FREQA and FREQB. The autoranging can be triggered on each frequency by setting the RNGSTART bit in PLLRANGINGA/B as shown in Figure 8 of
In your software, the best would be to autorange at each frequency once at the beginning, and then during operation quickly change from one channel to the other by already triggering auto-ranging from the known range that you previously calculated and stored in memory.
Changing across your three frequencies will be achievable.