I’m using AX5043, TCXO 16MHz(1ppm). My own made board.
Async_transmit for Tx and WOR_receive for Rx. Using 2 boards.
Packet transmission is OK for both direction. But the sensitivity is much lower than the test result of DVK.
I guess loss of PLL LOCK during Tx may be the cause.
Performing function axradio_init(), I successfully found VCORA(PLLRANGINGA) and VCOI(PLLVCOI) and set it.
But after axradio_init(), When POWMODE is set FULLTX, I can never achieve PLL lock(bit 6 of PLLRANGINGA).
Setting other mode like SYNTHTX or WORRX or FULLRX, lock is achieved and bit  of PLLRANGINGA is , somtimes.
I already read the issues below.
But still found no solution.
Please let me know what I’m missing.
With AX-Radioloab, is there any way to read out register value of DVK when running?