AX5043 (multipoint network with 1 base, point initiate connection with Base )

Hello !
Using AX5043 with TCXO NDK NT2016SA (NSC5318B)
Configuration:
Frequency range: 868 MHz
Modulation: PSK
Bitrate: 5 or 10 kSps (DIFF Enable)

Settings:
32 mobile points (temperature sensors) in LSB mode (2 way communication) point initiate connection.
Work in DRX mode (send data than waiting 200 ms answer from BS, than goes into deep sleep)
Data contain 33 bytes of settings and information about sensor

During test of my devices i found next: problems with frequency slide and RSSI measuring in LSB mode.

LSB test function (check the RSSI befor TX routine:)

int16_t RxCheckRSSI(void)
{
    uint8_t temp_rssi;
    int16_t rssi_out;

   ax5043_set_register(AX5043_PWRMODE, AX5043_PWRSTATE_POWERDOWN); //Wakeup from deep sleep
   ax5043_set_channel(EEP_REG[ADR_TXCHANNEL], EEP_REG[ADR_FREQ_OFFSET]);
   ax5043_set_registers(EEP_REG[ADR_FREQ_DEVIATION]); // setup current session bitrate (5 or 10 kBit)
   ax5043_set_registers_rx();
   ax5043_set_registers_rxcont();
   ax5043_pll_ranging();
   ax_irq_flag = 0;  // Drop IRQ flag
   ax5043_set_register(AX5043_FIFOSTAT, 3);
  ax5043_set_register(AX5043_IRQMASK0, 0x01);
  ax5043_set_register(AX5043_IRQMASK1, 0x00);
  ax5043_set_register(AX5043_PWRMODE, AX5043_PWRSTATE_FULL_RX);  // goes RX

    //For measure RSSI level correct, need wait 5...10mS, after switch into Full_Rx mode, in this time MCU sleep in WFI mode.
    timer_ax5043 = 10;
    while (timer_ax5043 > 0)
    {
        dog_sleep();
    }
    temp_rssi = ax5043_get_register(AX5043_RSSI);
    rssi_out = (uint8_t)(0xF7 + RSSIOFFSET) - temp_rssi;
    ax5043_set_register(AX5043_PWRMODE, AX5043_PWRSTATE_POWERDOWN);
    return rssi_out;
}

So i go to LSB and waiting RSSI, some time other device during TX mode but RSSI shows - 100 dDm, LSB func. returned OK, started TX and occured collision.
I understand it may be frequency slide.
In manual found another way measure RSSI:
AGCCOUNT and TRK_AMPLITUDE - it’s seems shows good changing RSSI channel level but i can not found mathematic function how that data can be interpritate into RSSI.

Another founded problem with frequency slide of some devices after collision (it’s seems like Auto Freq Correction (up to 2 kHz) but not return into channel ). if i switch power off\on - the device goes back into channel, immediatly.

My current settings:

void ax5043_set_registers(uint8_t dev)

{
  ax5043_set_register(AX5043_MODULATION, 0x04);
  ax5043_set_register(AX5043_ENCODING, 0x02);
  ax5043_set_register(AX5043_FRAMING, 0x26);
  ax5043_set_register(AX5043_PINFUNCSYSCLK, 0x01);
   ax5043_set_register(AX5043_PINFUNCDATA, 0x01);
  ax5043_set_register(AX5043_PINFUNCANTSEL, 0x01);
  ax5043_set_register(AX5043_PINFUNCPWRAMP, 0x07);  //TCXO mode
  ax5043_set_register(AX5043_WAKEUPXOEARLY, 0x01);
  ax5043_set_register(AX5043_IFFREQ1, 0x01);
  if (dev != 10)
  {
    ax5043_set_register(AX5043_IFFREQ0, 0x43);     //0xF8
    ax5043_set_register(AX5043_DECIMATION, 0x22);  //0x10
    ax5043_set_register(AX5043_RXDATARATE1, 0x27); //0x28
    ax5043_set_register(AX5043_RXDATARATE0, 0xD4); //0xA0
  }
  else
  {
    ax5043_set_register(AX5043_IFFREQ0, 0xF8);     //0xF8
    ax5043_set_register(AX5043_DECIMATION, 0x10);  //0x10
    ax5043_set_register(AX5043_RXDATARATE1, 0x28); //0x28
    ax5043_set_register(AX5043_RXDATARATE0, 0xA0); //0xA0
  }

  ax5043_set_register(AX5043_RXDATARATE2, 0x00);
  ax5043_set_register(AX5043_MAXDROFFSET2, 0x00);
  ax5043_set_register(AX5043_MAXDROFFSET1, 0x00);
  ax5043_set_register(AX5043_MAXDROFFSET0, 0x00);
  ax5043_set_register(AX5043_MAXRFOFFSET2, 0x80);
  ax5043_set_register(AX5043_MAXRFOFFSET1, 0x00);
  ax5043_set_register(AX5043_MAXRFOFFSET0, 0x00);
  ax5043_set_register(AX5043_AMPLFILTER, 0x00);
  ax5043_set_register(AX5043_RXPARAMSETS, 0xF4);
  ax5043_set_register(AX5043_AGCTARGET0, 0x84);
  if (dev != 10)
  {
    ax5043_set_register(AX5043_AGCGAIN0, 0xC5);  //0xB4
    ax5043_set_register(AX5043_TIMEGAIN0, 0x98); //0xA8
  }
  else
  {
    ax5043_set_register(AX5043_AGCGAIN0, 0xB4);  //0xB4
    ax5043_set_register(AX5043_TIMEGAIN0, 0xA8); //0xA8
  }
  ax5043_set_register(AX5043_DRGAIN0, 0xA2);
  ax5043_set_register(AX5043_PHASEGAIN0, 0xC3);
  ax5043_set_register(AX5043_FREQUENCYGAINA0, 0x46);
  ax5043_set_register(AX5043_FREQUENCYGAINB0, 0x0A);
  ax5043_set_register(AX5043_FREQUENCYGAINC0, 0x1F);
  ax5043_set_register(AX5043_FREQUENCYGAIND0, 0x1F);
  ax5043_set_register(AX5043_AMPLITUDEGAIN0, 0x06);
  ax5043_set_register(AX5043_FREQDEV10, 0x00);
  ax5043_set_register(AX5043_FREQDEV00, 0x00);
  ax5043_set_register(AX5043_BBOFFSRES0, 0x00);
  if (dev != 10)
  {
    ax5043_set_register(AX5043_AGCGAIN1, 0xC5); //0xB4
  }
  else
  {
    ax5043_set_register(AX5043_AGCGAIN1, 0xB4); //0xB4
  }
  ax5043_set_register(AX5043_AGCTARGET1, 0x84);
  ax5043_set_register(AX5043_AGCAHYST1, 0x00);
  ax5043_set_register(AX5043_AGCMINMAX1, 0x00);
  if (dev != 10)
  {
    ax5043_set_register(AX5043_TIMEGAIN1, 0x96); //0xA6
  }
  else
  {
    ax5043_set_register(AX5043_TIMEGAIN1, 0xA6); //0xA6
  }
  ax5043_set_register(AX5043_DRGAIN1, 0xA1);
  ax5043_set_register(AX5043_PHASEGAIN1, 0xC3);
  ax5043_set_register(AX5043_FREQUENCYGAINA1, 0x46);
  ax5043_set_register(AX5043_FREQUENCYGAINB1, 0x0A);
  ax5043_set_register(AX5043_FREQUENCYGAINC1, 0x1F);
  ax5043_set_register(AX5043_FREQUENCYGAIND1, 0x1F);
  ax5043_set_register(AX5043_AMPLITUDEGAIN1, 0x06);
  ax5043_set_register(AX5043_FREQDEV11, 0x00);
  ax5043_set_register(AX5043_FREQDEV01, 0x00);
  ax5043_set_register(AX5043_FOURFSK1, 0x16);
  ax5043_set_register(AX5043_BBOFFSRES1, 0x00);
  ax5043_set_register(AX5043_AGCGAIN3, 0xFF);
  ax5043_set_register(AX5043_AGCTARGET3, 0x84);
  ax5043_set_register(AX5043_AGCAHYST3, 0x00);
  ax5043_set_register(AX5043_AGCMINMAX3, 0x00);
  if (dev != 10)
  {
    ax5043_set_register(AX5043_TIMEGAIN3, 0x95); //0xA5
  }
  else
  {
    ax5043_set_register(AX5043_TIMEGAIN3, 0xA5); //0xA5
  }
  ax5043_set_register(AX5043_DRGAIN3, 0xA0);
  ax5043_set_register(AX5043_PHASEGAIN3, 0xC3);
  ax5043_set_register(AX5043_FREQUENCYGAINA3, 0x46);
  ax5043_set_register(AX5043_FREQUENCYGAINB3, 0x0A);
  ax5043_set_register(AX5043_FREQUENCYGAINC3, 0x1F);
  ax5043_set_register(AX5043_FREQUENCYGAIND3, 0x1F);
  ax5043_set_register(AX5043_AMPLITUDEGAIN3, 0x06);
  ax5043_set_register(AX5043_FREQDEV13, 0x00);
  ax5043_set_register(AX5043_FREQDEV03, 0x00);
  ax5043_set_register(AX5043_FOURFSK3, 0x16);
  ax5043_set_register(AX5043_BBOFFSRES3, 0x00);
  ax5043_set_register(AX5043_FSKDEV2, 0x00);
  ax5043_set_register(AX5043_FSKDEV1, 0x00);
  ax5043_set_register(AX5043_FSKDEV0, 0x00);
  ax5043_set_register(AX5043_MODCFGA, 0x05);
  ax5043_set_register(AX5043_TXRATE2, 0x00);
  if (dev != 10)
  {
    ax5043_set_register(AX5043_TXRATE1, 0x0C); //0x19
    ax5043_set_register(AX5043_TXRATE0, 0x19); //0x35
  }
  else
  {
    ax5043_set_register(AX5043_TXRATE1, 0x19); //0x19
    ax5043_set_register(AX5043_TXRATE0, 0x35); //0x35
  }
  ax5043_set_register(AX5043_PLLVCOI, 0x99);
  ax5043_set_register(AX5043_PLLRNGCLK, 0x04);
  ax5043_set_register(AX5043_BBTUNE, 0x0F);
  ax5043_set_register(AX5043_BBOFFSCAP, 0x77);
  ax5043_set_register(AX5043_PKTADDRCFG, 0x01);
  ax5043_set_register(AX5043_PKTLENCFG, 0x80);
  ax5043_set_register(AX5043_PKTLENOFFSET, 0x00);
  ax5043_set_register(AX5043_PKTMAXLEN, 0xC8);
  ax5043_set_register(AX5043_MATCH0PAT3, 0xAA);
  ax5043_set_register(AX5043_MATCH0PAT2, 0xCC);
  ax5043_set_register(AX5043_MATCH0PAT1, 0xAA);
  ax5043_set_register(AX5043_MATCH0PAT0, 0xCC);
  ax5043_set_register(AX5043_MATCH0LEN, 0x1F);
  ax5043_set_register(AX5043_MATCH0MAX, 0x1F);
  ax5043_set_register(AX5043_MATCH1PAT1, 0x55);
  ax5043_set_register(AX5043_MATCH1PAT0, 0x55);
  ax5043_set_register(AX5043_MATCH1LEN, 0x8A);
  ax5043_set_register(AX5043_MATCH1MAX, 0x0A);
  ax5043_set_register(AX5043_TMGTXBOOST, 0x3E);
  ax5043_set_register(AX5043_TMGTXSETTLE, 0x31);
  ax5043_set_register(AX5043_TMGRXBOOST, 0x3E);
  ax5043_set_register(AX5043_TMGRXSETTLE, 0x31);
  ax5043_set_register(AX5043_TMGRXOFFSACQ, 0x00);
  ax5043_set_register(AX5043_TMGRXCOARSEAGC, 0x7F);
  ax5043_set_register(AX5043_TMGRXRSSI, 0x03);
  ax5043_set_register(AX5043_TMGRXPREAMBLE2, 0x35);
  ax5043_set_register(AX5043_RSSIABSTHR, 0xE0);
  ax5043_set_register(AX5043_BGNDRSSITHR, 0x00);
  ax5043_set_register(AX5043_PKTCHUNKSIZE, 0x0D);
  ax5043_set_register(AX5043_PKTACCEPTFLAGS, 0x20);
  ax5043_set_register(AX5043_DACVALUE1, 0x00);
  ax5043_set_register(AX5043_DACVALUE0, 0x00);
  ax5043_set_register(AX5043_DACCONFIG, 0x00);
  ax5043_set_register(AX5043_REF, 0x03);
  ax5043_set_register(AX5043_XTALOSC, 0x04);
  ax5043_set_register(AX5043_XTALAMPL, 0x00);
  ax5043_set_register(AX5043_0xF1C, 0x07);
  ax5043_set_register(AX5043_0xF21, 0x68);
  ax5043_set_register(AX5043_0xF22, 0xFF);
  ax5043_set_register(AX5043_0xF23, 0x84);
  ax5043_set_register(AX5043_0xF26, 0x98);
  ax5043_set_register(AX5043_0xF34, 0x08);
  ax5043_set_register(AX5043_0xF35, 0x11);
  ax5043_set_register(AX5043_0xF44, 0x25);
  ax5043_set_register(AX5043_MODCFGP, 0xE1);
}
void ax5043_set_registers_tx(void)
{
 ax5043_set_register(AX5043_PLLLOOP, 0x07);
 ax5043_set_register(AX5043_PLLCPI, 0x12);
  ax5043_set_register(AX5043_PLLVCODIV, 0x20);
  ax5043_set_register(AX5043_XTALCAP, 0x00);
  ax5043_set_register(AX5043_0xF00, 0x0F);
  ax5043_set_register(AX5043_0xF18, 0x06);
}
void ax5043_set_registers_rx(void)
{
  ax5043_set_register(AX5043_PLLLOOP, 0x07);
  ax5043_set_register(AX5043_PLLCPI, 0x08);
  ax5043_set_register(AX5043_PLLVCODIV, 0x20);
  ax5043_set_register(AX5043_XTALCAP, 0x00);
  ax5043_set_register(AX5043_0xF00, 0x0F);
  ax5043_set_register(AX5043_0xF18, 0x06);
}
void ax5043_set_registers_rxwor(void)
{
  ax5043_set_register(AX5043_TMGRXAGC, 0x90);
  ax5043_set_register(AX5043_TMGRXPREAMBLE1, 0x19);
  ax5043_set_register(AX5043_PKTMISCFLAGS, 0x03);
}
void ax5043_set_registers_rxcont(void)
{

  ax5043_set_register(AX5043_TMGRXAGC, 0x00);
  ax5043_set_register(AX5043_TMGRXPREAMBLE1, 0x00);
  ax5043_set_register(AX5043_PKTMISCFLAGS, 0x00);
  ax5043_set_register(AX5043_RSSIREFERENCE, (uint8_t)(0xF7 + RSSIOFFSET)); //RSSI
  ax5043_set_register(AX5043_PKTSTOREFLAGS, 0x14);                         // Store RSSI and frequency offset
}
void ax5043_set_registers_rxcont_singleparamset(uint8_t dev) // dev = 5 or 10 (deviation )
{
  ax5043_set_register(AX5043_RXPARAMSETS, 0xFF);
  ax5043_set_register(AX5043_FREQDEV13, 0x00);
  ax5043_set_register(AX5043_FREQDEV03, 0x00);
  if (dev != 10)
  {
    ax5043_set_register(AX5043_AGCGAIN3, 0xEA);
  }
  else
  {
    ax5043_set_register(AX5043_AGCGAIN3, 0xD6);
  }
}