ADD5043-169 - Frequency Offset

Hi,

When the output of the AX5043EVB(ADD5043-xxx-2-GEVK) was measured with a spectrum analyzer, it was a different frequency with an offset to the frequency set by the AX-RadioLab.
When I measured the output with different output frequency settings, it was still output at different frequencies with the same offset.
At this time, the value of FREQA was set according to the formula introduced in AND9347/D.
When I tried to stop the VCO Auto-Ranging function from the source code generated by AX-RadioLab, the frequency set by AX-RadioLab came to be output.

Before;
COMMON>easy5043.c
1708: radio_write8(AX5043_REG_PLLRANGINGA, 0x18); // init ranging process starting from “range”
After;
COMMON>easy5043.c
1708: radio_write8(AX5043_REG_PLLRANGINGA, 0x08); // init ranging process starting from “range”

Why is there an offset in frequency when the VCO Auto-Ranging function is activated?
Also, what should I do to get the expected frequency without stopping the VCO Auto-Ranging function?

Best Regards,

Hi @satogata-s ,
what kind of offset are you measuring (Hz, KHz, MHz?)

  • Ax-RadioLab uses the same formula as in the datasheet to calculate FREQA/B so you should not find any difference between your calculation and the output from AX-RadioLab.
  • The radio has two routines where the frequency synthesizer ranges:
    • PLL Autoranging: this is done automatically by the internal HW and is used by the PLL to select the correct RNG (VCORA/B) that allows it to lock at the desired frequency. This routine is triggered by the PLLRANGINGA/B register and the ranging end can be detected either by polling or via interrupt.
  • VCO Ranging: this routine selects the best VCO current (VCOI) to have optimal noise. This dedicated app-note shows what external network is needed to perform such calibration VCO Current Calibration for Optimal Synthesizer Phase Noise AND9858-D.PDF

While you have to have a correct RNG to have the PLL locked, you can have the non-optimal VCOI at the cost of higher phase noise. In your case, as you see an ‘offset’ I think you may be running with an unlocked PLL. (check il PLL LOCK bit 6 is 1 during transmission).

I don’t understand what you mean by “stop the VCO Auto-Ranging”. The transition of PLLRANGING from 0x18 to 0x08 means that ranging has finished and VCORA was 8 and stayed 8. Once you start the PLL autoranging it stops automatically once its done (VCORA is set to 8 initially as it is the mid-value thus reducing the autoranging time. You could in principle start from any initial RNG e.g. PLLRANGINGA = 0x10 ).

Hi @georgi.gorine ,

Thank you for you response.

what kind of offset are you measuring (Hz, KHz, MHz?)

It is always seen 7MHz.

While you have to have a correct RNG to have the PLL locked, you can have the non-optimal VCOI at the cost of higher phase noise. In your case, as you see an ‘offset’ I think you may be running with an unlocked PLL. (check il PLL LOCK bit 6 is 1 during transmission).

What are the characteristics of the VCO Range selected by RNG depending on its value?
I understood that all I had to do was make sure the PLL LOCK bit 6 of the PLLRANGEA was 1 and if it was 0 I would do VCOI Calibration according to the app-note. Is this correct?

Best Regards,

Hi @satogata-s ,

It is always seen 7MHz.

If you consistently see 7 MHz, then its likely not an unlocked PLL but rather some wrong FREQA/B settings. The only source of error I could imagine would be that you have mistaken the Fxtal in the formula above.

I suggest you start from scratch, generating a new project in AX-RadioLab, and use the TEST project set to “Set CW” as explained on page 32 of the AX-RadioLab User Manual (AX-RadioLAB_user_manual.pdf (1.4 MB) ).

If you have not modified the PCB (meaning 48 MHz TCXO) then you will see a Carrier Wave at 868.30 MHz (default settings in RadioLab).

What are the characteristics of the VCO Range selected by RNG depending on its value?

The VCO is able to range autonomously (without an external inductor) over the frequency range 400 - 1000 MHz. The VCORA/B tune the LC tank of the VCO to sustain oscillations at the programmed frequency. You can try to increase the RNG manually and you will see that the PLL will start pulling until it unlocks.

I understood that all I had to do was make sure the PLL LOCK bit 6 of the PLLRANGEA was 1 and if it was 0 I would do VCOI Calibration according to the app-note. Is this correct?

The PLL LOCK bit indicates if the PLL is locked. If it gets unlocked you will need to re-run the PLL autoranging (setting RNG START). The VCOI Calibration is something else, and as explained in the app note above it is required to reduce the phase noise.
Note the following:

  • You should always first autorange and then calibrate VCOI → if RNG is totally off you can’t lock and hence you can’t calibrate VCOI.
  • Ranges overlap. You should be able to lock a given frequency with 2 adjacent RNG. Even in this case it is not guaranteed, that the optimal VCOI is the same for both RNG (although in practice they typically are very similar).

I checked the PLLLOCK bit. The programed software was TX1010 mode of BER test.

However, it seems that the PLL cannot be locked because the PLLLOCK bit does not become 1 and remains 0.

I tried with VCO calibration enabled, but PLLLOCK was 1 after the next process in easyax5043.c.

1704: radio_write8 (AX5043_REG_PLLRANGINGA, (axradio_phy_chanpllrng [i] & 0x0F));

After that, it seems that PLLLOCK is 0 during the comparison process of Vmax, Vmin and curtune in the axradio_calvcoi() function on line 1761.

I also checked the oscillation frequency of XTAL, but it oscillated at the expected oscillation frequency.

When the component constants of the board were returned to the factory shipped state (169MHz) and the TX1010 mode was programed and confirmed, a peak appeared near 173MHz with an offset of about 4MHz with respect to the carrier frequency setting.

I checked PLLLOCK with this setting, but it seems that the PLLLOCK bit remains 0 and the PLL does not LOCK even if I execute radio_write8 (AX5043_REG_PLLRANGINGA, 0x18) on line 1708 of easyax5043.c.

Is it possible for frequency offsets to occur even when the board component constants are shipped?

Hi @georgi.gorine ,

I reconfirmed the behavior of PLL LOCK. As a result, the PLL did not LOCK during the axradio_init() process, but the PLL locked during the axradio_set_mode() process.
Is it okay to understand the following when the PLL LOCK is completed?
PLL LOCK is not completed during axradio_init() processing, but is completed by executing axradio_set_mode() processing.

Also, when I reconfirmed the frequency of the crystal oscillator regarding the frequency offset, it was described as Q1 = 16MHz in the schematic of ADD5043-169-2-GEVK, but it was around 16.39MHz, which is different from that.
The BOM List in the Gerber.zip file of ADD5043-169-2-GEVK lists that NT2016SA is used for Q1, but the standard frequency of NT2016SA is 16.368MHz.
Could you tell me the correct product part number and frequency of TCXO Q1 used in ADD5043-169-2-GEVK.

When Fxtal was set to 16.368MHz in AX-Radio Lab, the expected frequency was output without any offset appearing in the carrier frequency.

Thanks and Best Regards,

Hi @georgi.gorine ,

Do you have an update for this topic?

Best Regards,

Hi @satogata-s ,
you are right about the TCXO frequency mismatch. We have unfortunately two batches of boards on the market. Both PCBs are marked as ADD5043-169-2-GEVK, but they can have mounted either a 16MHz (marked “16”) or 16.368 MHz (marked “163”). We are very sorry for the inconvenience.

Both TCXOs are from the NT2016SA family ( NT2016SA(Mobile Communications)/Temperature Compensated Crystal Oscillator (TCXO)/NDK). Currently seems like there are no 16MHz TCXO available, but there are for 16.368: NT2016SA-16.368000 MHZ-NTG1 NDK America, Inc. | Crystals, Oscillators, Resonators | DigiKey

This Fxtal mismatch explains why you saw a consistent frequency offset, as AX-RadioLab calculates FREQA from the Fxtal number inserted in the PHY Panel.

The only source of error I could imagine would be that you have mistaken the Fxtal in the formula above.

and therefore:

When Fxtal was set to 16.368MHz in AX-Radio Lab, the expected frequency was output without any offset appearing in the carrier frequency.

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