The memory map provided for the RSL15 device follows the standard Arm Cortex-M33 processor memory layout. All memory instances and memory-mapped elements are accessible through this memory map, as shown in the "Default RSL15 Memory Map" figure.
The address ranges are in hexadecimal format. The following subsections provide a brief description and usage of each area. These areas are as follows:
- Program ROM, as described in the Program ROM Chapter of the RSL15 Firmware Reference Manual
- Flash Memory
- Data RAM
- Other memory mapped areas
Flash Memory
RSL15 contains a flash memory instance that provides the following areas that can be written through the flash memory interface:
Code Flash
An area of flash optimized for use as larger (2 KB) blocks of memory. This area is typically used to store program code.
Data Flash
An area of flash optimized for use as smaller (256 B) blocks of memory. This area is typically used to store static data or additional program code, including memory reserved for the Arm CryptoCell-312 (DEU reserved), and Bluetooth bond records (bond info).
Non-Volatile Records
A set of manufacturing-specific and other non-volatile records. These records are used to store elements used by the Arm CryptoCell-312 (NVR0 to NVR3), manufacturing and calibration records (NVR7, MNVR), and user records (NVR4 to NVR6).
Redundancy Sectors
A set of four redundancy sectors that can be used to replace two code flash and two data flash sectors.
For more information about the flash memory, see Flash.
Data Memory
The 32-bit data memory is distributed into DRAM and BB DRAM memory instances.
- 64 KB of DRAM are shared between the Bluetooth stack and the user application. The DRAM is subdivided into 8 instances of 8192 bytes (2048 words) as DRAM0 - DRAM7. These instances are used to store any type of data needed for user applications.
- 16 KB of BB DRAM act as the exchange memory between the Arm Cortex-M33 processor and the baseband controller. The BB DRAM is subdivided into 2 instances of 8192 bytes (2048 words) as BB_DRAM0 and BB_DRAM1. These instances are directly accessible by the Arm Cortex-M33 processor and the DMA, parallel to the baseband controller.
Other Memory Mapped Areas
Peripherals and Interfaces
Memory-mapped registers on the peripheral bus are addressed between 0x4000 0000 and 0x400F FFFF (1 MB). This region contains the registers that are used to control various peripherals, interfaces, and other system components.
Private Peripherals
Memory-mapped registers on the private peripheral bus are addressed between 0xE000 0000 and 0xE00F FFFF. This region contains registers related to the Arm Cortex-M33 processor.