ROM Initialization Sequence

The ROM is split into two main parts:

  1. The low level initialization and setup, which is written in assembler: this part is responsible for ensuring that the power supplies are set up, and that memory instances are enabled for default power-up conditions.
  2. The higher level functionality implemented in C dealing with the various peripherals, life cycle states and security features: these are defined in more detail in Security Subsystem.

The ROM initialization sequence is shown graphically in the "ROM Initialization Sequence Flowchart" figure. The flowchart describes the various paths through the boot sequence, taking into account the possible life cycle states and power modes.

Figure: ROM Initialization Sequence Flowchart

The "Boot Options" table shows the available boot options.

Table: Boot Options

ACS_BOOT_CFG

CC312AO

Results

BOOT_ROT_BYPASS_ENABLE

Enable

Pass but with cold boot

BOOT_ROT_BYPASS_DISABLE

Enable

Pass but with cold boot

BOOT_ROT_BYPASS_DISABLE

Disable

Fail with CCAO_REBOOT_RESET_FLAG_SET in ACS_RESET_STATUS

BOOT_ROT_BYPASS_ENABLE

Disable

Fail with watchdog reset in boot ROM

ROM Basic Initialization

The basic system initialization function is called once the power supplies and memories have been set to known default states. At this stage the RAM is enabled and the C stack is available for use.

The primary sequence of this initialization is as follows:

  • Set up the NVIC to allow only NMI and Hard Fault exceptions.
  • Disable the MPU, bus, and usage faults, forcing them to be always promoted to hard faults.
  • Disable all of the external interrupts and clear all pending status indicators.
  • Assign the NMI to a constant low source.
  • Stop any running flash or flash copier operations.
  • Reset the GPIOs.
  • Enable all JTAG pins.
  • Disable Pad Retention Mode.
  • Configure the watchdog timer for a maximum timeout, and refresh.
  • Disable DMA.
  • Configure Non Secure code zone.
  • Disable the SAU and set the ALLNS to zero so everything is secure.
  • Configure the non-secure accesses to RAM and peripherals as disabled.
  • Make sure the flash is not busy before setting up the RC.
  • Configure the RC for 12 MHz.
  • Select the RC oscillator as the system clock.
  • Set up the various clock pre-scalars.
  • Disable RF access.
  • Disable the baseband interface.
  • Enable all memories.
  • Ensure that the Arm CryptoCell-312 (CC312) is enabled and ready to run.
  • Set the system core clock variable and flash delays, indicating that the device is configured to use the 12 MHz RC oscillator.