To prevent possible issues inherent in flash technology, an Error Correcting Code (ECC) ensures the integrity of the flash content, as follows:
- When writing to the flash, the ECC bits are automatically generated by the flash interface and appended to the data.
- When reading from the flash, the error detection/correction is applied automatically.
The algorithm relies on the (38, 32) extended Hamming code, where 32 data bits are extended by 6 parity bits to form a 38-bit word. This is a Single Error Correcting (SEC) code, which allows correction of a single bit error.
The flash ECC bit generation and the error detection and correction are performed on the fly by a dedicated hardware block with no incurred latency on the read/write operation, as shown in the "Flash Write and Read Operations Sequence with ECC Enabled" figure.
Figure: Flash Write and Read Operations Sequence with ECC Enabled
When writing to the flash memory with ECC enabled (the FLASH_ECC_CTRL_CMD_ECC_CTRL field in the FLASH_ECC_CTRL register), the 6 parity bits are first computed over the 32-bit FLASH_DATA[0] registers using the extended Hamming encoding scheme. The 32-bit data from the register is left-extended with the resulting 6 parity bits, and written into the flash as a 38-bit word.
When reading from the flash memory with ECC enabled, the 38-bit word is read from the flash address, and the ECC bits are computed over the 38-bit data read from the flash using the extended Hamming encoding scheme. The computed ECC bits are compared to the six parity bits and are then read from the flash.
No errors
If no difference is observed, the status register FLASH_ECC_STATUS is not updated.
One error
If the bit to be corrected is inside the 32-bit data, one error has been detected. The data is corrected before being used, the FLASH_ECC_STATUS_ECC_COR_ERROR_CNT_STATUS bit in the FLASH_ECC_STATUS register is set, the corrupted flash address is saved in the FLASH_ECC_ERROR_ADDR register, and the value of FLASH_ECC_COR_ERROR_CNT counter is incremented by one. When the counter becomes equal to or greater than FLASH_ECC_CTRL_ECC_COR_CNT_INT_THRESHOLD, a FLASH_ECC_INT interrupt is generated.
More than one error
If the corrected bit is outside the 32-bit data, the detected ECC error cannot be corrected. The FLASH_ECC_STATUS_ECC_UNCOR_ERROR_CNT_STATUS bit in the FLASH_ECC_STATUS register is set, the corrupted flash address is saved in the FLASH_ECC_ERROR_ADDR register, the value of the FLASH_ECC_UNCOR_ERROR_CNT counter is incremented by one, and a FLASH_ECC_INT interrupt is generated.
The ECC status flags and FLASH_ECC_ERROR_ADDR register can be cleared using the FLASH_ECC_STATUS_ECC_COR_ERROR_CNT_CLEAR, FLASH_ECC_STATUS_ECC_UNCOR_ERROR_CNT_CLEAR, and FLASH_ECC_STATUS_ECC_ERROR_ADDR_CLEAR bits from the FLASH_ECC_STATUS register.
The total number of detected errors is reported in the FLASH_ECC_UNCOR_ERROR_CNT register. The counter saturates at 255, and can be reset by setting the FLASH_ECC_STATUS_ECC_UNCOR_ERROR_CNT_CLEAR bit in the FLASH_ECC_STATUS register.
The total number of corrected errors is reported in the FLASH_ECC_COR_ERROR_CNT register. The counter saturates at 255, and can be reset by setting the FLASH_ECC_STATUS_ECC_COR_ERROR_CNT_CLEAR bit in the FLASH_ECC_STATUS register.