Peripherals

The RSL15 system has a number of peripherals to support auxiliary non-RF tasks. These peripherals are described briefly in the sections below, and in detail in Activity Counters.

Additional peripherals that are only accessible to the Arm Cortex-M33 processor have been defined by Arm and integrated into the RSL15 system. These blocks are described in Private Peripherals.

Activity Counter

The activity counters help to analyze how long the RSL15 system has been running, and how much the CPU and the flash have been used by the application in a period of time. This is useful information for estimating and optimizing the power consumption of the application.

Asynchronous Clock Counter

The asynchronous clock counter measures the timing of a clock signal, such as STANDBYCLK or a clock provided on a GPIO input, relative to the system clock.

CRC

This block provides an implementation of two standard cyclic redundancy code (CRC) algorithms (CRC-CCITT and CRC-32 - IEEE 802.3), which can be used to ensure the integrity of a user application's code and data.

DMA Controller

The Direct Memory Access (DMA) Controller allows background transfers between peripherals and memories without processor intervention. The system can be in the idle low power state, with the processor waiting for an interrupt or event, or in use for other computational tasks while the transfer occurs. The DMA is connected to the processor, peripherals, and RAM memories, and has four independent channels.

Flash Copier

The flash copier supports several operations on data that has been stored to flash memory:

• A background copy of data stored in the flash to another area in memory
• A background copy of flash data to the CRC block for data integrity validation
• A comparison operation over a block with a fixed value, used primarily to validate if data has been erased or has been cleared by being overwritten to zero

Timers

There are four independent 24-bit timers that can operate as single-shot, multi-shot, or free-run. Interrupt or GPIO output can be configured with timer value capture on timer expiration.

Watchdog

The watchdog timer must be reloaded at regular intervals. If it is not refreshed and the timer expires, a reset is issued to the system. The watchdog timer is disabled when the RSL15 system is connected to an external debugger, but otherwise cannot be disabled.