*FDG6316P at Temp. Electrical Model
*--------------------------------------------
.SUBCKT FDG6316P 20 10 30 50
*20=DRAIN 10=GATE 30=SOURCE 50=VTEMP
Rg 10 11x 1
Rdu 12x 1 1u
M1 2 1 4x 4x DMOS L=1u W=1u
.MODEL DMOS PMOS(VTO=-0.7 KP=5
+THETA=0.25 VMAX=8.5E5 LEVEL=3)
Cgs 1 5x 120p
Rd 20 4 4.2E-2
Dds 4 5x DDS
.MODEL DDS D(M=6.04E-1 VJ=1.15 CJO=35p)
Dbody 20 5x DBODY
.MODEL DBODY D(IS=5.64E-8 N=1.522514 RS=.002803 TT=9.77n)
Ra 4 2 4.2E-2
Rs 5x 5 0.5m
Ls 5 30 0.5n
M2 1 8 6 6 INTER
E2 8 6 4 1 2
.MODEL INTER PMOS(VTO=0 KP=10 LEVEL=1)
Cgdmax 7 4 199p
Rcgd 7 4 10meg
Dgd 4 6 DGD
Rdgd 4 6 10meg
.MODEL DGD D(M=3.5E-1 VJ=1.24E-1 CJO=199p)
M3 7 9 1 1 INTER
E3 9 1 4 1 -2
*ZX SECTION
EOUT 4x 6x poly(2) (1x,0) (3x,0) 0 0 0 0 1
FCOPY 0 3x VSENSE 1
RIN 1x 0 1G
VSENSE 6x 5x 0
RREF 3x 0 10m
*TEMP SECTION
ED 101 0 VALUE {V(50,100)}
VAMB 100 0 25
EKP 1x 0 101 0 .07
*VTO TEMP SECTION
EVTO 102 0 101 0 .0005
EVT 11x 12x 102 0 1
*DIODE THEMO BREAKDOWN SECTION
EBL VB1 VB2 101 0 .08
VBLK VB2 0 12
D DB1 20 DBLK
.MODEL DBLK D(IS=1E-14 CJO=.1p RS=.1)
EDB 0 DB1 VB1 0 1
.ENDS FDG6316P
*FDG6316P (Rev.A1) 4/18/02 **ST