.SUBCKT FDMS7650DC 2 1 3
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**      Fairchild Discrete Modeling Group                       **
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**      Website         www.fairchildsemi.com\models            **
**      Scott Pearson   scott.pearson@fairchildsemi.com         **
**      Chris Hanas     chris.hanas@fairchildsemi.com           **
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**      (C) Copyright 2009 Fairchild Semiconductor Corporation  **
**                      All rights reserved                     **
**                                                              **
**                      FDMS7650DC Spice model                  **
**                      Revision RevA, 04 Jan 2010              **
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*Nom Temp 25 deg C
Dbody 7 5 DbodyMOD
Dbreak 5 11 DbreakMOD
Lgate 1 9 1.594e-9
Ldrain 2 5 0.004e-9
Lsource 3 7 0.33e-9
RLgate 1 9 15.94
RLdrain 2 5 0.04
RLsource 3 7 3.3
Rgate 9 6 1.4
* Shielded gate
D1         100 5 D_SG_cap
D2         100 101 D_SG_cap
R1         101 7  3.37
C1         6 101  1130e-12
.MODEL D_SG_cap D (IS=1e-9 n=1 RS=4.0e-3 CJO=8.6e-9 M=0.6 t_abs=25)
It 7 17 1
Ebreak 11 7 17 7 32.57
Rbreak 17 7 RbreakMOD 1
.MODEL RbreakMOD RES (TC1=0.53e-3 TC2=-0.9e-6)
.MODEL DbodyMOD D (IS=9.99e-12 n=1 RS=0.55e-3 TRS1=1.5e-3 TRS2=1e-6
+ CJO=4.16e-9 M=0.4 TT=1e-9 XTI=4) ;CJO=8.323e-9
.MODEL DbreakMOD D (RS=30e-3 TRS1=1e-3 TRS2=1e-6 )
Rsource 7a 7 0.408e-3
Rdrain 5 16 RdrainMOD 0.2e-3
.MODEL RdrainMOD RES (TC1=7.5e-3 TC2=20e-6)
M_BSIM3 16 6 7a 7a Bsim3 W=23.67 L=1.57e-6 NRS=0 NRD=0
.MODEL Bsim3 NMOS (LEVEL=7 VERSION=3.1 MOBMOD=3 CAPMOD=2 paramchk=1 NQSMOD=0
*Process Parameters
+ TOX=500e-10 ;Oxide thickness
+ XJ=0.16e-6 ;Channel depth
+ NCH=2.0e17 ;Channel concentration
*Channel Current
+ U0=1050 VSAT=500000 DROUT=1.2
+ DELTA=0.18 PSCBE2=0.00001 RSH=0.408e-3
*Threshold voltage
+ VTH0=1.965
*Sub-threshold characteristics
+ VOFF=-0.12 NFACTOR=1.19
*Junction diodes and Capacitance
+ LINT=0.495e-6 DLC=0.495e-6
+ CGSO=45e-12 CGSL=10e-12 CGDO=0.5e-12 CGDL=90e-12 ;CGSO=90e-12
+ CJ=0 CF=0 CKAPPA=1.25
* Temperature parameters
+ KT1=-1.8 KT2=0 UA1=4e-9
+ NJ=10)
.ENDS