.SUBCKT FDMC8030 2 1 3
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**      Fairchild Discrete Modeling Group                       **
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**      (C) Copyright 2009 Fairchild Semiconductor Corporation  **
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**                      FDMC8030 Spice model                     **
**                    Revision RevB, November15 2011                **
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*Nom Temp 25 deg C
Dbody 7 5 DbodyMOD 
Dbreak 5 11 DbreakMOD 
Lgate 1 9 0.578e-9
Ldrain 2 5 0.006e-9
Lsource 3 7 0.121e-9
RLgate 1 9 5.78
RLdrain 2 5 0.06
RLsource 3 7 1.21
Rgate 9 6 2.28
* Shielded  Gate  
D_D1 100 5 D_SG_cap
D_D2 100 101 D_SG_cap
R_R1 101 7 6.44
C_C1 6 101 200e-12
.MODEL D_SG_cap D (IS=1e-9 n=1 RS=5e-3 CJO=1.45e-9 M=0.6 t_abs=25);14.4e-9  
It 7 17 1
Ebreak 11 7 17 7 44
Rbreak 17 7 RbreakMOD 1 
.MODEL RbreakMOD RES (TC1=0.65e-3 TC2=-1e-6)
.MODEL DbodyMOD D (IS=4.2e-12 n=1 RS=4.573e-3 TRS1=4.9e-3 TRS2=1e-6 
+ CJO=0.13e-9 M=0.1 TT=3e-9 XTI=1)
.MODEL DbreakMOD D (RS=30e-3 TRS1=1e-3 TRS2=1e-6 )
Rsource 7a 7 0.916e-3
Rdrain 5 16 RdrainMOD 4.876e-3
.MODEL RdrainMOD RES (TC1=10e-3 TC2=20e-6)
M_BSIM3 16 6 7a 7a Bsim3 W=2.12 L=0.624e-6 NRS=0 NRD=0
.MODEL Bsim3 NMOS (LEVEL=7 VERSION=3.1 MOBMOD=3 CAPMOD=2 paramchk=1 NQSMOD=0
*Process Parameters
+ TOX=500e-10 ;Oxide thickness
+ XJ=0.22e-6 ;Channel depth
+ NCH=1.4e17 ;Channel concentration
*Channel Current
+ U0=600 VSAT=500000 DROUT=1.2
+ DELTA=0.05 PSCBE2=0 RSH=0.916e-3
*Threshold voltage
+ VTH0=1.7
*Sub-threshold characteristics
+ VOFF=-0.1 NFACTOR=1.1
*Junction diodes and Capacitance
+ LINT=0.11e-6 DLC=0.11e-6 
+ CGSO=360e-12 CGSL=0 CGDO=1e-12 CGDL=190e-12 
+ CJ=0 CF=0 CKAPPA=0.3
* Temperature parameters 
+ KT1=-1.1 KT2=0 UA1=6e-9
+ NJ=10)
.ENDS   
*