* PSpice Model Editor - Version 16.3.0
*$
.SUBCKT FDMC7696 2 1 3	
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**      Fairchild Discrete Modeling Group                       **
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**      Website         www.fairchildsemi.com\models            **
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**      (C) Copyright 2009 Fairchild Semiconductor Corporation  **
**                      All rights reserved                     **
**                                                              **
**                      FDMC7696 Spice model                     **
**                      Revision RevA, 27 Sep 2010              **
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*Nom Temp 25 deg C		
Dbody 7 5 DbodyMOD 		
Dbreak 5 11 DbreakMOD 		
Lgate 1 9 2.992e-9		
Ldrain 2 5 0.004e-9		
Lsource 3 7 0.877e-9		
RLgate 1 9 29.92		
RLdrain 2 5 0.04		
RLsource 3 7 8.77		
Rgate 9 6 1.6		
D_D1 100 5 D_SG_cap		
D_D2 100 101 D_SG_cap		
R_R1 101 7 7.5		
C_C1 6 101 80e-12		
.MODEL D_SG_cap D (IS=1e-9 n=1 RS=17.6e-3 CJO=1.25e-9 M=0.6 t_abs=25) 		
It 7 17 1		
Ebreak 11 7 17 7 32.8		
Rbreak 17 7 RbreakMOD 1 		
.MODEL RbreakMOD RES (TC1=0.5e-3 TC2=-0.2e-6)		
.MODEL DbodyMOD D (IS=0.47e-12 n=1 RS=4.6e-3 TRS1=1.5e-3 TRS2=1e-6 		
+ CJO=0.3e-9 M=0.36 TT=3e-9 XTI=3) ;0.88		
.MODEL DbreakMOD D (RS=30e-3 TRS1=1e-3 TRS2=1e-6 )		
Rsource 7a 7 2.348e-3		
Rdrain 5 16 RdrainMOD 4.8e-3		
.MODEL RdrainMOD RES (TC1=4e-3 TC2=8e-6)		
M_BSIM3 16 6 7a 7a Bsim3 W=2.48425 L=0.8e-6 NRS=0 NRD=0		
.MODEL Bsim3 NMOS (LEVEL=7 VERSION=3.1 MOBMOD=3 CAPMOD=2 paramchk=1 NQSMOD=0		
+ TOX=500e-10 		
+ XJ=0.16e-6 		
+ NCH=1.56e17 
+ U0=990 VSAT=500000 DROUT=1.2		
+ DELTA=0.27 PSCBE2=0.00001 RSH=2.348e-3		
+ VTH0=2.36		
+ VOFF=-0.19 NFACTOR=1.3		
+ LINT=0.135e-6 DLC=0.135e-6 		
+ CGSO=130e-12 CGSL=0 CGDO=12e-12 CGDL=110e-12 ;162 		
+ CJ=0 CF=0 CKAPPA=0.25		
+ KT1=-1.1 KT2=0 UA1=2.7e-9		
+ NJ=10)		
.ENDS   		
*$