.SUBCKT FDMC7660dc 2 1 3

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**      Fairchild Discrete Modeling Group                       **
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**      Website         www.fairchildsemi.com\models            **
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**      (C) Copyright 2009 Fairchild Semiconductor Corporation  **
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**                      FDMC7660DC Spice model                **
**                      Revision RevA, 26 MARCH 2010               **
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*Nom Temp 25 deg C		
Dbody 7 5 DbodyMOD 		
Dbreak 5 11 DbreakMOD 		
Lgate 1 9 0.517e-9		
Ldrain 2 5 0.005e-9		
Lsource 3 7 0.056e-9		
RLgate 1 9 5.17		
RLdrain 2 5 0.05		
RLsource 3 7 0.56		
Rgate 9 6 0.82	
D_D1 100 5 D_SG_cap		
D_D2 100 101 D_SG_cap		
R_R1 101 7 1.94		
C_C1 6 101 112e-12		
.MODEL D_SG_cap D (IS=2e-9 n=1 RS=4e-3 CJO=4.8e-9 M=0.6 t_abs=25) 		
It 7 17 1		
Ebreak 11 7 17 7 32.6	
Rbreak 17 7 RbreakMOD 1 		
.MODEL RbreakMOD RES (TC1=0.5e-3 TC2=-1e-6)		
.MODEL DbodyMOD D (IS=3.5e-12 n=1 RS=0.9e-3 TRS1=1.5e-3 TRS2=1e-6 		
+ CJO=1.0e-9 M=0.35 TT=1e-9 XTI=2)
.MODEL DbreakMOD D (RS=30e-3 TRS1=1e-3 TRS2=1e-6 )		
Rsource 7a 7 0.373e-3		
Rdrain 5 16 RdrainMOD 1.0e-3		
.MODEL RdrainMOD RES (TC1=3.5e-3 TC2=12e-6)		
M_BSIM3 16 6 7a 7a Bsim3 W=7.98 L=1.57e-6 NRS=0 NRD=0		
.MODEL Bsim3 NMOS (LEVEL=7 VERSION=3.1 MOBMOD=3 CAPMOD=2 paramchk=1 NQSMOD=0		
+ TOX=500e-10		
+ XJ=0.16e-6 		
+ NCH=2.15e17 	
+ U0=1050 VSAT=500000 DROUT=1.2		
+ DELTA=0.17 PSCBE2=0.00001 RSH=0.367e-3		
+ VTH0=1.85; 1.48		
+ VOFF=-0.1 NFACTOR=1.1		
+ LINT=0.495e-6 DLC=0.495e-6 		
+ CGSO=56e-12 CGSL=0.0 CGDO=0.5e-12 CGDL=170e-12 		
+ CJ=0 CF=0 CKAPPA=0.5		
+ KT1=-1.4 KT2=0 UA1=2.8e-9; KT1=-1.2 KT2=0 UA1=3e-9		
+ NJ=10)		
.ENDS