.SUBCKT FDMC612PZ 2 1 3
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**      Fairchild Discrete Modeling Group                       **
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**      (C) Copyright 2013 Fairchild Semiconductor Corporation  **
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**                      FDMC612PZ Spice model                	**
**                    Revision RevA, 13 May 2014                **
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*Nom Temp 25 deg C
Dbody 5 7 DbodyMOD
Dbreak 7 11 DbreakMOD 
Lgate 1 9 1.735e-9
Ldrain 2 5 0.005e-9
Lsource 3 7 0.283e-9
RLgate 1 9 17.35
RLdrain 2 5 0.05
RLsource 3 7 2.83
Rgate 9 6 4.38
D1 100 5 D_Sh_cap
D2 100 101 D_Sh_cap
Rshield 9 101 8.9
Cshield 6 101 10e-12
.MODEL D_Sh_cap D (IS=1e-9 n=1 RS=5e-3 CJO=0.95e-9 M=0.24 t_abs=25)
It 7 17 1
Ebreak 5 11 17 7 -23.15
Rbreak 17 7 RbreakMOD 1 
.MODEL RbreakMOD RES (TC1=0.9e-3 TC2=-0.5e-6)
.MODEL DbodyMOD D (IS=9.6e-12 n=1 RS=4.8e-3 TRS1=1.5e-3 TRS2=1e-6
+ CJO=0.45e-9 M=0.8 TT=3e-9 XTI=1)
.MODEL DbreakMOD D (RS=30e-3 TRS1=1e-3 TRS2=1e-6 )
Rsource 7a 7 1.279e-3
Rdrain 5 16 RdrainMOD 3.0e-3
.MODEL RdrainMOD RES (TC1=2.0e-3 TC2=0.1e-6)
M_BSIM3 16 6 7a 7a Bsim3 W=6.3 L=0.75e-6 NRS=0 NRD=0
.MODEL Bsim3 PMOS (LEVEL=7 VERSION=3.1 MOBMOD=3 CAPMOD=2 paramchk=1 NQSMOD=0
+ TOX=233e-10 
+ XJ=0.15e-6 
+ NCH=1.74e17 
+ U0=250 VSAT=500000 DROUT=1.8
+ DELTA=0.28 PSCBE2=0 RSH=1.279e-3
+ VTH0=-0.895
+ VOFF=-0.1 NFACTOR=1.1
+ LINT=0.19e-6 DLC=0.19e-6 
+ CGSO=365e-12 CGSL=0 CGDO=105e-12 CGDL=190e-12 
+ CJ=0 CF=0 CKAPPA=0.85
+ KT1=-0.75 KT2=0 UA1=13.5e-9
+ NJ=10)
.ENDS
*