.SUBCKT FDMB3800N 2 1 3
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**      Fairchild Discrete Modeling Group                       **
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**      Website         www.fairchildsemi.com\models            **
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**      (C) Copyright 2011 Fairchild Semiconductor Corporation  **
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**                      FDMB3800N Spice model                   **
**                    Revision RevA, 1 Oct 2013                 **
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*Nom Temp=25 deg C
*7 Aug 2013 Rev.A
Dbody 7 5 DbodyMOD
Dbreak 5 11 DbreakMOD
Lgate 1 9 0.442n
Ldrain 2 5 0.01n
Lsource 3 7 0.458n
RLgate 1 9 4.42
RLdrain 2 5 0.1
RLsource 3 7 4.58
Rgate 9 6 3.0
It 7 17 1
Ebreak 11 7 17 7 33
Rbreak 17 7 RbreakMOD 1
.MODEL RbreakMOD RES (TC1=9e-4 TC2=-1e-6)
.MODEL DbodyMOD D (IS=0.5e-12 n=1.03 RS=18m TRS1=1.5e-3 TRS2=1e-6
+ CJO=1.5e-10 M=0.4 TT=3n XTI=3 )
.MODEL DbreakMOD D (RS=8e-2 TRS1=1e-3 TRS2=1e-6)
Rsource 77 7 8.49m
Rdrain 5 16 RdrainMOD 20.2m
.MODEL RdrainMOD RES (TC1=4.4e-3 TC2=8.5e-6)
M_BSIM3 16 6 77 77 Bsim3 W=0.56 L=0.9u NRS=0 NRD=0
.MODEL  Bsim3 NMOS (LEVEL=7 VERSION=3.1 MOBMOD=3 CAPMOD=2 paramchk=1 NQSMOD=0
*Process Parameters
+ TOX=400e-10 ;Oxide thickness
+ XJ=0.97u ;Channel depth
+ NCH=1.8e17 ;Channel concentration
*Channel Current
+ U0=850 VSAT=8e5 DROUT=1.8
+ DELTA=0.30 PSCBE2=0 RSH=8.49m
*Threshold voltage
+ VTH0=1.65
*Sub-threshold characteristics
+ VOFF=-0.2 NFACTOR=1.05
*Junction diodes and Capacitance
+ LINT=0.165u DLC=0.165u
+ CGSO=150p CGSL=0 CGDO=43p CGDL=430p
+ CJ=0 CF=0 CKAPPA=0.28
* Temperature parameters
+ KT1=-0.9 KT2=0 UA1=3.0e-9
+ NJ=10
.ENDS FDMB3800N