* PSpice Model Editor - Version 16.3.0
*$
.SUBCKT FDMA3028N 2 1 3	
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**      Fairchild Discrete Modeling Group                       **
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**      Website         www.fairchildsemi.com\models            **
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**      (C) Copyright 2009 Fairchild Semiconductor Corporation  **
**                      All rights reserved                     **
**                                                              **
**                      FDMA3028N Spice model                   **
**                      Revision RevA, 31 January 2011          **
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*Nom Temp 25 deg C		
Dbody 7 5 DbodyMOD 		
Dbreak 5 11 DbreakMOD 		
Lgate 1 9 0.657e-9		
Ldrain 2 5 0.011e-9		
Lsource 3 7 0.297e-9		
RLgate 1 9 6.57		
RLdrain 2 5 0.11		
RLsource 3 7 2.97		
Rgate 9 6 2.75		
It 7 17 1		
Ebreak 11 7 17 7 32.9		
Rbreak 17 7 RbreakMOD 1 		
.MODEL RbreakMOD RES (TC1=0.8e-3 TC2=0.01e-6)		
.MODEL DbodyMOD D (IS=4e-12 n=1 RS=35e-3 TRS1=1.8e-3 TRS2=1e-6 		
+ CJO=11.8e-12 M=0.12 TT=3e-9 XTI=0.1)		
.MODEL DbreakMOD D (RS=80e-3 TRS1=1e-3 TRS2=0 )		
Rsource 7a 7 12.256e-3		
Rdrain 5 16 RdrainMOD 32e-3		
.MODEL RdrainMOD RES (TC1=4.6e-3 TC2=7e-6)		
M_BSIM3 16 6 7a 7a Bsim3 W=0.39 L=0.89e-6 NRS=0 NRD=0		
.MODEL Bsim3 NMOS (LEVEL=7 VERSION=3.1 MOBMOD=3 CAPMOD=2 paramchk=1 NQSMOD=0		
*Process Parameters		
+ TOX=240e-10 ;Oxide thickness		
+ XJ=0.52e-6 ;Channel depth		
+ NCH=1.32e17 ;Channel concentration		
*Channel Current		
+ U0=790 VSAT=200000 DROUT=2.5		
+ DELTA=0.09 PSCBE2=0 RSH=12.256e-3		
*Threshold voltage		
+ VTH0=0.945		
*Sub-threshold characteristics		
+ VOFF=-0.1 NFACTOR=1		
*Junction diodes and Capacitance		
+ LINT=0.12e-6 DLC=0.12e-6 		
+ CGSO=59e-12 CGSL=0 CGDO=25e-12 CGDL=590e-12 		
+ CJ=0 CF=0 CKAPPA=0.5		
* Temperature parameters 		
+ KT1=-0.62 KT2=0 UA1=5.5e-9		
+ NJ=10)		
.ENDS   		
* 	
*$