* PSpice Model Editor - Version 16.0.0
*$
.SUBCKT FDG410NZ 2 1 3
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**      Fairchild Discrete Modeling Group                       **
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**      Website         www.fairchildsemi.com\models            **
**      Scott Pearson   scott.pearson@fairchildsemi.com         **
**      Sylvie Tran     sylvie.tran@fairchildsemi.com           **
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**      (C) Copyright 2008 Fairchild Semiconductor Corporation  **
**                      All rights reserved                     **
**                                                              **
**                      FDG410NZ Spice model                    **
**                      Revision RevA, 18 Feb 2009 (ST)         **
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*Nom Temp 25 deg C
Dbody 7 5 DbodyMOD
Dbreak 5 11 DbreakMOD
Lgate 1 9 0.408e-9
Ldrain 2 5 0.1e-9
Lsource 3 7 0.278e-9
RLgate 1 9 4.08
RLdrain 2 5 1
RLsource 3 7 2.78
Rgate 9 6 2.9
It 7 17 1
Ebreak 11 7 17 7 22
Rbreak 17 7 RbreakMOD 1
.MODEL RbreakMOD RES (TC1=0.85e-3 TC2=-1e-6)
.MODEL DbodyMOD D (IS=4.7e-11 n=1 RS=72.1e-3 TRS1=2e-3 TRS2=1e-6
+ CJO=0.159e-9 M=0.5 TT=0.1e-9 XTI=-6)
.MODEL DbreakMOD D (RS=30e-3 TRS1=1e-3 TRS2=0)
Rsource 7a 7 7.402e-3
Rdrain 5 16 RdrainMOD 38.5e-3 
.MODEL RdrainMOD RES (TC1=4e-3 TC2=1e-6)
M_BSIM3 16 6 7a 7a Bsim3 W=0.42 L=0.93e-6 NRS=0 NRD=0
.MODEL Bsim3 NMOS (LEVEL=7 VERSION=3.1 MOBMOD=3 CAPMOD=2 paramchk=1 NQSMOD=0
*Process Parameters
+ TOX=160e-10 ;Oxide thickness
+ XJ=0.42e-6 ;Channel depth
+ NCH=1.8e17 ;Channel concentration
*Channel Current
+ U0=700 VSAT=5e5 DROUT=1.2
+ DELTA=0.02 PSCBE2=1e-5 RSH=7.402e-3
*Threshold voltage
+ VTH0=0.8
*Sub-threshold characteristics
+ VOFF=-0.1 NFACTOR=1
*Junction diodes and Capacitance
+ LINT=0.145e-6 DLC=0.145e-6
+ CGSO=90e-12 CGSL=0-12 CGDO=58e-12 CGDL=548e-12
+ CJ=0 CF=0 CKAPPA=0.5
* Temperature parameters
+ KT1=-0.56 KT2=0 UA1=8.5e-9
+ NJ=10)
.ENDS
*$