* PSpice Model Editor - Version 16.3.0
*$
.SUBCKT FDD86250 2 1 3
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**      Fairchild Discrete Modeling Group                       **
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**      Website         www.fairchildsemi.com\models            **
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**      (C) Copyright 2009 Fairchild Semiconductor Corporation  **
**                      All rights reserved                     **
**                                                              **
**                      FDD86250 Spice model                   **
**                      Revision RevA, 27 December 2010         **
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*Nom Temp 25 deg C		
Dbody 7 5 DbodyMOD 		
Dbreak 5 11 DbreakMOD 		
Lgate 1 9 5.88e-9		
Ldrain 2 5 0.1e-9		
Lsource 3 7 2.457e-9		
RLgate 1 9 58.8		
RLdrain 2 5 1		
RLsource 3 7 24.57		
Rgate 9 6 0.59
* Shielded  Gate  		
D_D1 100 5 D_SG_cap		
D_D2 100 101 D_SG_cap		
R_R1 101 7 0.49		
C_C1 6 101 127e-12		
.MODEL D_SG_cap D (IS=1e-9 n=1 RS=5e-3 CJO=1.42e-9 M=0.6 t_abs=25) 		
It 7 17 1		
Ebreak 11 7 17 7 159.5		
Rbreak 17 7 RbreakMOD 1 		
.MODEL RbreakMOD RES (TC1=0.75e-3 TC2=-0.7e-6)		
.MODEL DbodyMOD D (IS=4.1e-12 n=1 RS=3.4e-3 TRS1=2.5e-3 TRS2=1e-6 		
+ CJO=0.57e-9 M=0.55 TT=3e-9 XTI=2.7) ;1.7		
.MODEL DbreakMOD D (RS=8e-3 TRS1=1e-3 TRS2=1e-6 )		
Rsource 7a 7 0.965e-3		
Rdrain 5 16 RdrainMOD 15.3e-3		
.MODEL RdrainMOD RES (TC1=8.4e-3 TC2=23e-6)		
M_BSIM3 16 6 7a 7a Bsim3 W=4.1 L=1.1e-6 NRS=0 NRD=0		
.MODEL Bsim3 NMOS (LEVEL=7 VERSION=3.1 MOBMOD=3 CAPMOD=2 paramchk=1 NQSMOD=0		
*Process Parameters		
+ TOX=1000e-10 ;Oxide thickness		
+ XJ=0.54e-6 ;Channel depth		
+ NCH=0.8e17 ;Channel concentration		
*Channel Current		
+ U0=700 VSAT=500000 DROUT=1.8		
+ DELTA=0.04 PSCBE2=0 RSH=0.965e-3		
*Threshold voltage		
+ VTH0=3.7		
*Sub-threshold characteristics		
+ VOFF=-0.4 NFACTOR=1.25		
*Junction diodes and Capacitance		
+ LINT=0.19e-6 DLC=0.19e-6 		
+ CGSO=126e-12 CGSL=0 CGDO=0.3e-12 CGDL=108e-12 ;157		
+ CJ=0 CF=0 CKAPPA=0.25		
* Temperature parameters 		
+ KT1=-1.7 KT2=0 UA1=3.3e-9		
+ NJ=10)		
.ENDS   		
* 		
*$