.SUBCKT FDC8884 2 1 3 ****************************************************************** ** Fairchild Discrete Modeling Group ** ****************************************************************** ** Website www.fairchildsemi.com\models ** ****************************************************************** ** (C) Copyright 2012 Fairchild Semiconductor Corporation ** ** All rights reserved ** ** ** ** FDC8884 Spice model ** ** Revision RevA, 18 July 2012 ** ****************************************************************** *Nom Temp 25 deg C Dbody 7 5 DbodyMOD Dbreak 5 11 DbreakMOD Lgate 1 9 1.117e-9 Ldrain 2 5 0.004e-9 Lsource 3 7 0.167e-9 RLgate 1 9 11.17 RLdrain 2 5 0.04 RLsource 3 7 1.67 Rgate 9 6 4.78 D_D1 100 5 D_SG_cap D_D2 100 101 D_SG_cap R_R1 101 7 11.76 C_C1 6 101 32e-12 .MODEL D_SG_cap D (IS=1e-9 n=1 RS=5e-3 CJO=0.36e-9 M=0.5 t_abs=25) It 7 17 1 Ebreak 11 7 17 7 32.85 Rbreak 17 7 RbreakMOD 1 .MODEL RbreakMOD RES (TC1=0.7e-3 TC2=-1e-6) .MODEL DbodyMOD D (IS=1e-12 n=1 RS=16e-3 TRS1=1e-3 TRS2=1e-6 + CJO=0.093e-9 M=0.35 TT=3e-9 XTI=4) .MODEL DbreakMOD D (RS=30e-3 TRS1=1e-3 TRS2=1e-6 ) Rsource 7a 7 0.489e-3 Rdrain 5 16 RdrainMOD 15.5e-3 .MODEL RdrainMOD RES (TC1=2.9e-3 TC2=4e-6) M_BSIM3 16 6 7a 7a Bsim3 W=0.88 L=0.48e-6 NRS=0 NRD=0 .MODEL Bsim3 NMOS (LEVEL=7 VERSION=3.1 MOBMOD=3 CAPMOD=2 paramchk=1 NQSMOD=0 + TOX=500e-10 + XJ=0.195e-6 + NCH=1.24e17 + U0=670 VSAT=500000 DROUT=1.2 + DELTA=0.3 PSCBE2=0 RSH=0.489e-3 + VTH0=2.28 + VOFF=-0.17 NFACTOR=1.7 + LINT=0.09e-6 DLC=0.09e-6 + CGSO=144e-12 CGSL=0 CGDO=13e-12 CGDL=105e-12 + CJ=0 CF=0 CKAPPA=1 + KT1=-1.2 KT2=0 UA1=4e-9 + NJ=10) .ENDS *