* PSpice Model Editor - Version 16.3.0

*$
.SUBCKT FDC6401N 2 1 3
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**      Fairchild Discrete Modeling Group                       **
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**      Website         www.fairchildsemi.com\models            **
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**      (C) Copyright 2009 Fairchild Semiconductor Corporation  **
**                      All rights reserved                     **
**                                                              **
**                      FDC6401N Spice model                    **
**                      Revision RevA, 25 March 2010              **
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*Nom Temp 25 deg C
Dbody 7 5 DbodyMOD
Dbreak 5 11 DbreakMOD
Lgate 1 9 0.628e-9
Ldrain 2 5 0.1e-9
Lsource 3 7 0.368e-9
RLgate 1 9 6.28
RLdrain 2 5 1
RLsource 3 7 3.68
Rgate 9 6 3.15
It 7 17 1
Ebreak 11 7 17 7 23.3
Rbreak 17 7 RbreakMOD 1
.MODEL RbreakMOD RES (TC1=0.65e-3 TC2=-0.5e-6)
.MODEL DbodyMOD D (IS=2.5e-12 n=1 RS=44e-3 TRS1=1.5e-3 TRS2=0
+ CJO=11e-11 M=0.4 TT=3e-9 XTI=1)
.MODEL DbreakMOD D (RS=80e-3 TRS1=1e-3 TRS2=0)
Rsource 7a 7 13.679e-3
Rdrain 5 16 RdrainMOD 25.4e-3
.MODEL RdrainMOD RES (TC1=5.3e-3 TC2=3e-6)
M_BSIM3 16 6 7a 7a Bsim3 W=0.29 L=1.5e-6 NRS=0 NRD=0
.MODEL Bsim3 NMOS (LEVEL=7 VERSION=3.1 MOBMOD=3 CAPMOD=2 paramchk=1 NQSMOD=0
*Process Parameters
+ TOX=300e-10 ;Oxide thickness
+ XJ=0.9e-6 ;Channel depth
+ NCH=1.5e17 ;Channel concentration
*Channel Current
+ U0=750 VSAT=500000 DROUT=1.8
+ DELTA=0.1 PSCBE2=0.00001 RSH=13.679e-3
*Threshold voltage
+ VTH0=0.8
*Sub-threshold characteristics
+ VOFF=-0.05 NFACTOR=1.2
*Junction diodes and Capacitance
+ LINT=0.45e-6 DLC=0.45e-6
+ CGSO=493e-12 CGSL=0 CGDO=56e-12 CGDL=600e-12
+ CJ=0 CF=0 CKAPPA=0.9
* Temperature parameters
+ KT1=-0.6 KT2=0 UA1=3.5e-9
+ NJ=10)
.ENDS FDC6401N
* Rev.0_SB		2/22/2010
*$