*MODEL FILE NAME: LCX06T.SPI
**********************************************************************
* FAIRCHILD I/O SPICE DECK FOR LCX06
**********************************************************************
*
* MODEL NAME: LCX06N.SPI
* DATE CREATED/UPDATED: CREATED 05-15-00
* REVISION NUMBER: 1.0 (BETA MODEL, NON-CORRELATED TO SILICON)
* DESIGNERS INITIALS: CK
*
* MODEL TYPE: I/O SUBCIRCUIT,  PACKAGE MODEL INCLUDED 14 PIN SOIC, 14 PIN TSSOP
* PROCESS TYPE: NOMINAL
* TEMP RANGE:25C TO 150C
*
* VERIFIED ON AVANTI STAR-HSPICE VERSION 98.4
*
********************************************************************************
* DISCLAIMER:
********************************************************************************
*
* FAIRCHILD SEMICONDUCTOR CORPORATION HEREBY GRANTS THE USER OF THIS
* SPICE MODEL A NON-EXCLUSIVE, NONTRANSFERABLE LICENSE TO USE THIS
* SPICE MODEL UNDER THE FOLLOWING TERMS.  BEFORE USING THIS
* SPICE MODEL, THE USER SHOULD READ THIS LICENSE.
*
* THE USER IS GRANTED THIS LICENSE ONLY TO USE THE SPICE MODEL AND IS
* NOT GRANTED RIGHTS TO SELL, LOAN, RENT, LEASE OR LICENSE THE SPICE
* MODEL IN WHOLE OR IN PART, OR IN MODIFIED FORM TO ANYONE OTHER THAN
* USER. USER MAY MODIFY THE SPICE MODEL TO SUIT ITS SPECIFIC
* APPLICATIONS BUT RIGHTS TO DERIVATIVE WORKS AND SUCH MODIFICATIONS
* SHALL BELONG TO FAIRCHILD.
*
* THIS SPICE MODEL IS PROVIDED ON AN 'AS IS' BASIS AND FAIRCHILD SEMICONDUCTOR
* MAKES ABSOLUTELY NO WARRANTY WITH RESPECT TO THE INFORMATION CONTAINED
* HEREIN.  FAIRCHILD DISCLAIMS AND CUSTOMER WAIVES ALL WARRANTIES,
* EXPRESS OR IMPLIED, INCLUDING WARRANTIES OF MERCHANTABILITY OR FITNESS
* FOR A PARTICULAR PURPOSE. THE ENTIRE RISK AS TO QUALITY AND PERFORMANCE
* IS WITH THE CUSTOMER.  ACCORDINGLY, IN NO EVENT SHALL THE COMPANY BE
* LIABLE FOR ANY DAMAGES, WHETHER IN CONTRACT OR TORT, INCLUDING ANY
* LOST PROFITS OR OTHER INCIDENTAL, CONSEQUENTIAL, EXEMPLARY, OR
* PUNITIVE DAMAGES ARISING OUT OF THE USE OR APPLICATION OF THE SPICE
* MODEL PROVIDED IN THIS PACKAGE.  FURTHER, FAIRCHILD RESERVES THE RIGHT
* TO MAKE CHANGES WITHOUT NOTICE TO ANY PRODUCT HEREIN TO IMPROVE,
* RELIABILITY, FUNCTION, OR DESIGN.  FAIRCHILD DOES NOT CONVEY ANY LICENSE
* UNDER PATENT RIGHTS OR ANY OTHER INTELLECTUAL PROPERTY RIGHTS,
* INCLUDING THOSE OF THIRD PARTIES.
*
* FAIRCHILD IS NOT OBLIGATED TO PROVIDE MAINTENANCE OR SUPPORT FOR
* THE LICENSED SPICE MODEL.
*
********************************************************************************
* SPECIAL NOTES:
********************************************************************************
*
*
* BETA HSPICE MODEL DISCLAIMER
*
* THIS HSPICE MODEL IS CLASSIFIED AS A 'BETA MODEL ONLY'.  'BETA MODELS' HAVE
* BEEN VERIFIED FOR OPERATION AND FUNCTIONALITY ONLY.  THESE MODELS HAVE NOT
* BEEN CORRELATED TO CURRENT PROCESSES OR DESIGN CHARACTERISTICS.
* IT IS BELIEVED THAT THESE 'BETA MODELS' WERE REPRESENTATIVE OF THE DESIGN
* AND PROCESS AT THE TIME  OF THEIR INTRODUCTION THOUGH NO LEVEL OF ACCURACY
* IS IMPLIED.
*
* ALL 'BETA MODELS' ARE CLEARLY MARKED 'BETA MODEL ONLY'.  'BETA MODELS' ARE
* USED AT YOUR OWN RISK AND SHOULD BE TREATED AS AN APPROXIMATE REPRESENTATION
* OF THE SILICON DEVICE.  THERE IS NO SUPPORT AVAILABLE FOR 'BETA MODELS'.
* IF YOU HAVE QUESTIONS OR CONCERN REGARDING THIS POLICY PLEASE CONTACT YOUR
* LOCAL SALES REPRESENTATIVE, THE FAIRCHILD SEMICONDUCTOR TECHNICAL RESPONSE
* CENTER (1-877-564-4263) OR VISIT THE FAIRCHILD SEMICONDUCTOR WEBSITE AT
* HTTP://WWW.FAIRCHILDSEMI.COM
*
*
*                       ALL MATERIAL CONTAINED HEREIN IS
*                  COPYRIGHT 1999 - FAIRCHILD SEMICONDUCTOR CORPORATION
*
********************************************************************************
*
* THIS MODEL MAY CONTAIN MODIFIED FUNCTIONALITY. IT MAY NOT REPRESENT TIMING
* CHARACTERISTICS OF THE LCX06 OR ANY OTHER FAIRCHILD SEMICONDUCTOR DEVICE.
* IT IS REPRESENTATIVE OF THE BASIC INPUT, OUTPUT CHARACTERISTICS OF THE LCX06
* DEVICE
*
* THE TERMINALS OF THIS NETLIST ARE DESCRIBED AS FOLLOWS:
*      IN      =       INPUT PIN
*      OUT     =       OUTPUT PIN
*      VCCEXT  =       EXTERNAL POWER SOURCE
*      GNDEXT  =       EXTERNAL GROUND
*
*
***********************************************************************
***********************************************************************
* TEST FORCING FUNCTIONS AND LOADS.  PLEASE UNCOMMENT THESE TO TEST SPICE
* DECK (INCLUDING .END).
***********************************************************************
*COUT OUT GNDEXT  15E-12 M=1.0
*VCC3 VCCEXT GNDEXT  3.3
*VCC6 VTERM GNDEXT 6.0
*VIN IN GNDEXT  PULSE 0.0 3.0 1E-9 3E-9 3E-9 30E-9 60E-9
*RUP OUT VTERM 500.0
*RDWN OUT GNDEXT 500
*VGND GNDEXT 0 0
*
*************************
* TEST TRANSIENT ANALYSIS
*************************
*.TRAN  1.00000E-10 10.00000E-08 START= 1.00000E-09
*.TEMP    25.0000
*.OPTION  INGOLD=2 POST=2 METHOD = GEAR SEARCH = LCX06TM0'
*+        PROBE=0
*+        GMINDC = 1.00000E-15
*+        GMIN   = 1.00000E-15
*
*************************************
* TEMPLATE TOP CALLS FOR:
* DIE, TSSOP PACKAGE OR SOIC PACKAGE
*************************************
*
* XDIE IN OUT GNDEXT VCCEXT LCX06TDI
*XPKG IN OUT GNDEXT VCCEXT LCX06TMT
*XPKG IN OUT GNDEXT VCCEXT LCX06TM0
*
***********************************************************************
***********************************************************************
* SPICE SUBCIRCUITS FOR PACKAGE PINS
***********************************************************************
* THESE FILES ARE SUBCIRCUIT SPICE MODELS FOR THE FAIRCHILD SEMICONDUCTOR
* LOGIC DEVICES. THEY ARE INTENDED FOR USE AS PACKAGE
* MODELS WHICH WILL ACCURATELY REPRESENT THE CHARACTERISTICS OF THE
* INDICATED PACKAGE PINS.
*
* THESE MODEL FILES CAN BE USED INDEPENDENTLY FROM TEMPERATURE.
*
* THE TERMINALS OF THESE SUBCIRCUITS ARE LABELLED AS FOLLOWS:
*       EXT         NODE    1
*       INT         NODE    3
*       GNDI        NODE    GND
*
* SPECIAL NOTES:
*   1. THE EXT NODE IS THE NODE WHICH IS USED TO CONNECT EXTERNAL LOADS
*      TO THE PACKAGE.  THE INT NODE IS THE NODE WHICH IS USED TO CONNECT
*      INPUT OR OUTPUT SUBCIRCUITS TO THE PACKAGE ELEMENTS.  IN OTHER
*      WORDS, THIS IS THE BOND PAD NODE.
*   2. THE GNDI NODE IS A GROUND NODE WHICH IS INTERNAL TO A PACKAGE.  ALL
*      SUBCIRCUITS WHICH REPRESENT INTERNAL CIRCUITS IN A PACKAGE SHOULD
*      HAVE THEIR GNDI NODES CONNECTED TOGETHER.  THE GNDI NODE SHOULD NOT
*      BE CONNECTED TO A GROUND REFERENCE NODE WHICH IS USED WITH
*      EXTERNAL VOLTAGE GENERATORS.
*   3. THE INDUCTORS WHICH ARE LABELLED AS L$2 REPRESENT AVERAGE BOND
*      WIRE INDUCTANCES.  THEY ARE NOT PART OF THE INDUCTANCE MATRIX FOR
*      THE PACKAGE LEAD FINGERS.
***********************************************************************
*
***********************************************************************
*   14 PIN SOIC PACKAGE (150 MILS WIDE) - CORNER PIN
***********************************************************************
.SUBCKT SOIC14CRNR 1 3 GND
R$1 1 2 0.07
R$2 2 3 10000000
L$1 2 4 1.30NH
L$2 4 3 0.50NH
C$1 3 GND 0.10PF
.ENDS
*
***********************************************************************
*   14 PIN SOIC PACKAGE (150 MILS WIDE) - CENTER PIN
***********************************************************************
.SUBCKT SOIC14MID 1 3 GND
R$1 1 2 0.064
R$2 2 3 10000000
L$1 2 4 .75NH
L$2 4 3 0.39NH
C$1 3 GND 0.025PF
.ENDS
*
***********************************************************************
*   14 PIN TSSOP PACKAGE - CORNER PIN
***********************************************************************
.SUBCKT TSSOP14CRNR 1 3 GND
R$1 1 2 0.10
R$2 2 3 10000000
L$1 2 4 3.00NH
L$2 4 3 0.50NH
C$1 3 GND 0.22PF
.ENDS
*
***********************************************************************
*   14 PIN TSSOP PACKAGE - CENTER PIN
***********************************************************************
.SUBCKT TSSOP14MID 1 3 GND
R$1 1 2 0.08
R$2 2 3 10000000
L$1 2 4 1.50NH
L$2 4 3 0.50NH
C$1 3 GND 0.10PF
.ENDS
*
.SUBCKT LCX06TMT I0 O0 GNDEXT VCCEXT
XI1 I0 I0I GNDEXT TSSOP14MID
XI2 O0 O0I GNDEXT TSSOP14MID
XI3 VCCEXT VCCI GNDEXT TSSOP14CRNR
XI4 GNDEXT GNDI GNDEXT TSSOP14CRNR
XI5 I0I O0I GNDI VCCI LCX06TDI
.ENDS LCX06TMT
.SUBCKT LCX06TM0 I0 O0 GNDEXT VCCEXT
XI1 I0 I0I GNDEXT SOIC14MID
XI2 O0 O0I GNDEXT SOIC14MID
XI3 VCCEXT VCCI GNDEXT SOIC14CRNR
XI4 GNDEXT GNDI GNDEXT SOIC14CRNR
XI5 I0I O0I GNDI VCCI LCX06TDI
.ENDS LCX06TM0
.SUBCKT LCX06TDI IN OUT PWRN PWRP
XIA IN OUT PWRN PWRP LCXPATH
.ENDS LCX06TDI
*
*
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