*Model File name : FXWA9306f ************************************************************************ * FAIRCHILD I/O SPICE DECK FOR FXWA9306 ************************************************************************ * * Model Name: FXWA9306 * Date Created/Updated :12/30/2011 * Revision Number: 1.0 * Created By: Weiming Sun * * Model Type: I/O Subcircuit * Package models included: MICROPAK_8 * Process: fast * Verified on Avanti Star-HSPICE Version 2001.4 ******************************************************************************** * DISCLAIMER: ******************************************************************************** * * Fairchild Semiconductor Corporation hereby grants the user of this * SPICE model a non-exclusive, nontransferable license to use this * SPICE model under the following terms. Before using this * SPICE model, the user should read this license. * * The user is granted this license only to use the SPICE model and is * not granted rights to sell, loan, rent, lease or license the SPICE * model in whole or in part, or in modified form to anyone other than * user. User may modify the SPICE model to suit its specific * applications but rights to derivative works and such modifications * shall belong to Fairchild. * * This SPICE model is provided on an "AS IS" basis and Fairchild Semiconductor * makes absolutely no warranty with respect to the information contained * herein. FAIRCHILD DISCLAIMS AND CUSTOMER WAIVES ALL WARRANTIES, * EXPRESS OR IMPLIED, INCLUDING WARRANTIES OF MERCHANTABILITY OR FITNESS * FOR A PARTICULAR PURPOSE. The entire risk as to quality and performance * is with the Customer. ACCORDINGLY, IN NO EVENT SHALL THE COMPANY BE * LIABLE FOR ANY DAMAGES, WHETHER IN CONTRACT OR TORT, INCLUDING ANY * LOST PROFITS OR OTHER INCIDENTAL, CONSEQUENTIAL, EXEMPLARY, OR * PUNITIVE DAMAGES ARISING OUT OF THE USE OR APPLICATION OF THE SPICE * model provided in this package. Further, Fairchild reserves the right * to make changes without notice to any product herein to improve, * reliability, function, or design. Fairchild does not convey any license * under patent rights or any other intellectual property rights, * including those of third parties. * * Fairchild is not obligated to provide maintenance or support for * the licensed SPICE model. * ******************************************************************************** * SPECIAL NOTES: ******************************************************************************** * * * Beta HSPICE Model Disclaimer * * This HSPICE model is classified as a "Beta Model Only". "Beta Models" have * been verified for operation and functionality ONLY. These models HAVE NOT * been correlated to current processes or design characteristics. * It is believed that these "Beta Models" were representative of the design * and process at the time of their introduction though no level of accuracy * is implied. * * All "Beta Models" are clearly marked "BETA MODEL ONLY". "Beta Models" are * used at your own risk and should be treated as an approximate representation * of the silicon device. There is no support available for "Beta Models". * If you have questions or concern regarding this policy please contact your * local sales representative, the Fairchild Semiconductor Technical Response * Center (1-877-564-4263) or visit the Fairchild Semiconductor website at * http://www.fairchildsemi.com * ** All material contained herein is * COPYRIGHT 2011 - Fairchild Semiconductor Corporation * * * ******************************************************************************** * * THIS MODEL MAY CONTAIN MODIFIED FUNCTIONALITY. IT MAY NOT REPRESENT TIMING * CHARACTERISTICS OF THE FXWA9306 OR ANY OTHER FAIRCHILD SEMICONDUCTOR DEVICE. * IT IS REPRESENTATIVE OF THE BASIC INPUT, OUTPUT CHARACTERISTICS OF THE * FXWA9306 DEVICE. * * The terminals of this netlist are described as follows: ******************************************************************************** * * * A0 = input * A1 = input * OE = enable * B0 = output * B1 = output * VCCEXT = Power Pin * VCCB = Power Pin * GNDEXT = Ground Pin * * * * Spice Subcircuits for Package Pins * ************************************************************************************ * * These files are subcircuit spice models for the Fairchild Semiconductor * logic devices. They are intended for use as package models * which will accurately represent the characteristics of the * indicated package pins. * * These model files can be used independently from temperature. * * The terminals of these subcircuits are labelled as follows: * EXT node 1 * I node 3 * GNDI node GND * * SPECIAL NOTES: * 1. The EXT node is the node which is used to connect external loads * to the package. The INT node is the node which is used to connect * input or output subcircuits to the package elements. In other * words, this is the bond pad node. * 2. The GNDI node is a ground node which is internal to a package. All * subcircuits which represent internal circuits in a package should * have their GNDI nodes connected together. The GNDI node should NOT * be connected to a ground reference node which is used with * external voltage generators. * 3. The inductors which are labelled as L$2 represent average bond * wire inductances. They are not part of the inductance matrix for * the package lead fingers. * *********************************************************************************** * PACKAGES * ******************************************************************** * micropak PACKAGE - CORNER PIN ******************************************************************** .SUBCKT microCRNR 1 3 GND R$1 1 2 53e-3 L$1 2 4 0.56e-9 L$2 4 5 0.055e-9 R$2 5 3 0.57e-3 C$1 4 GND 0.0375e-12 C$2 5 GND 0.0375e-12 .ENDS * ******************************************************************** * micropak PACKAGE - CENTER PIN ******************************************************************** .SUBCKT microMID 1 3 GND R$1 1 2 43e-3 L$1 2 4 0.46e-9 L$2 4 5 0.062e-9 R$2 5 3 0.63e-3 C$1 4 GND 0.055e-12 C$2 5 GND 0.055e-12 .ENDS * *********************************************************************** * END OF PACKAGES *********************************************************************** * *********************************************************************** * TEST FORCING FUNCTIONS * (Uncomment the following to test including .END) *********************************************************************** * *VPWR0 VCCEXT GNDEXT 3.3 *VPWR1 VCCB GNDEXT 5 *VDATA0 A0 GNDEXT PULSE 3.3 0.0 5E-9 2.0E-9 2.0E-9 47.5E-9 100E-9 *VDATA1 A1 GNDEXT PULSE 0.0 3.3 5E-9 2.0E-9 2.0E-9 47.5E-9 100E-9 *VENB0 OE GNDEXT DC 5.0 *VGND0 GNDEXT 0 DC 0 * ********************************************************************* * LOAD ********************************************************************* *VTERM0 TERM GNDEXT 10 *RTERM0 TERM B0 300 *R0 B0 GNDEXT 300 *CTERM0 B0 GNDEXT 15p *RTERM1 TERM B1 600 *R1 B1 GNDEXT 600 *CTERM1 B1 GNDEXT 15p ********************************************************************** * OPTIONS ********************************************************************** * *.temp = -40 *.OPTION INGOLD=2 ARTIST=2 PSF=2 post=2 *+ PROBE=0 *+ GMINDC = 1.00000E-12 *+ GMIN = 1.00000E-12 *+ method = gear LVLTIM = 2 chgtol = 1e-9 *.plot V(A0) V(A1) V(OE) V(B0) V(B1) *.tran 1.0ns 200ns * ************************************************************************* * END OF TEST FORCING FUNCTIONS ************************************************************************* * *********************************************************************** * XDIE is the top call for the subckt for the die only (no package model) * XPKG is the top call for the subckt for slice with package model * * Uncomment Top call desired *********************************************************************** * * XDIE A0 A1 OE B0 B1 VCCEXT VCCB GNDEXT FXWA9306f * * ************************************************************************* * PACKAGE CALL ************************************************************************* * *XPKG A0 A1 OE B0 B1 VCCEXT VCCB GNDEXT FXWA9306fl8 .SUBCKT FXWA9306fl8 A0 A1 OE B0 B1 VCCEXT VCCB GNDEXT X0 A0 A0I GNDEXT MICROCRNR X1 A1 A1I GNDEXT MICROMID X2 OE OEI GNDEXT MICROMID X3 B0 B0I GNDEXT MICROMID X4 B1 B1I GNDEXT MICROCRNR X5 VCCEXT VCCEXTI GNDEXT MICROMID X6 VCCB VCCBI GNDEXT MICROCRNR X7 GNDEXT GNDEXTI GNDEXT MICROCRNR X8 A0I A1I OEI B0I B1I VCCEXTI VCCBI GNDEXTI FXWA9306f .ENDS FXWA9306fl8 * ************************************************************************* * .INCLUDE "/home/fsbe/fs35bc/cadenv2X6X2_beta1/models/hspiceD/init.lib" .LIB "/home/fsbe/fs35bc/cadenv2X6X2_beta1/models/hspiceD/SPECIFY_FLOW.lib" dual_gate .LIB "/home/fsbe/fs35bc/cadenv2X6X2_beta1/models/hspiceD/hspiceD.lib" ff .subckt biasiso gnd oe oe_int vcca vccb xr2 vccb vccbi gnd RWA l=8e-6 w=2e-6 m=1 mm=0 xr1 oe_int oe gnd RNP l=3e-6 w=4e-6 m=1 mm=0 xr0 vcca vccai gnd RWA l=8e-6 w=2e-6 m=1 mm=0 xm8 gnd gnd gnd gnd net042 gnd NWAFFLEI_5V l=500e-9 cgs=450e-9 nrow=20 ncolumn=24 m=1 xm6 vccb oe_int vcca net056 net042 gnd NWAFFLEI_5V l=500e-9 cgs=450e-9 nrow=19 ncolumn=24 m=1 xm2 gnd vccai net056 net056 net042 gnd NWAFFLEI_5V l=500e-9 cgs=700e-9 nrow=5 ncolumn=5 m=1 xm4 gnd vccbi net056 net056 net042 gnd NWAFFLEI_5V l=500e-9 cgs=700e-9 nrow=5 ncolumn=5 m=1 xm0 vccb oe_int vcca net056 net042 gnd NWAFFLEI_5V l=500e-9 cgs=450e-9 nrow=19 ncolumn=24 m=1 xm3 vcca vccbi net042 net042 PMOSB_5V l=500e-9 w=10e-6 n=1 c2gs=300e-9 c2gd=300e-9 m=1 mm=0 xm1 vccb vccai net042 net042 PMOSB_5V l=500e-9 w=10e-6 n=1 c2gs=300e-9 c2gd=300e-9 m=1 mm=0 .ends biasiso .subckt ESDIn_2X_5V pad pwrn xm0 pad net5 pwrn pwrn NESDBS_5V l=600e-9 w=420e-6 n=12 c2gs=1e-6 c2gd=1.8e-6 m=1 mm=0 xm1 pad net5 pwrn pwrn NESDBS_5V l=600e-9 w=420e-6 n=12 c2gs=1e-6 c2gd=1.8e-6 m=1 mm=0 xr0 net5 net8 pwrn RWA l=13.1e-6 w=3e-6 m=1 mm=0 xr1 net8 pwrn pwrn RWA l=13.1e-6 w=3e-6 m=1 mm=0 xd0 net5 pad pwrn DPD l=4e-6 w=10.5e-6 m=1 mm=0 .ends ESDIn_2X_5V .subckt SWI a b gnd oe_int xr1 ai a gnd RWA l=8e-6 w=2e-6 m=1 mm=0 xr5 bi b gnd RWA l=8e-6 w=2e-6 m=1 mm=0 xm6 b ai net023 net023 PMOSB_5V l=500e-9 w=10e-6 n=1 c2gs=300e-9 c2gd=300e-9 m=1 mm=0 xm7 a bi net023 net023 PMOSB_5V l=500e-9 w=10e-6 n=1 c2gs=300e-9 c2gd=300e-9 m=1 mm=0 xm10 b oe_int a net071 net023 gnd NWAFFLEI_5V l=500e-9 cgs=450e-9 nrow=19 ncolumn=24 m=1 xm8 gnd gnd gnd gnd net023 gnd NWAFFLEI_5V l=500e-9 cgs=450e-9 nrow=20 ncolumn=24 m=1 xm4 gnd ai net071 net071 net023 gnd NWAFFLEI_5V l=500e-9 cgs=450e-9 nrow=5 ncolumn=5 m=1 xm2 b oe_int a net071 net023 gnd NWAFFLEI_5V l=500e-9 cgs=450e-9 nrow=19 ncolumn=24 m=1 xm5 gnd bi net071 net071 net023 gnd NWAFFLEI_5V l=500e-9 cgs=450e-9 nrow=5 ncolumn=5 m=1 .ends SWI .subckt ESDout_5V pad pwrn xn1 pad net15 pwrn pwrn NESDB_5V l=600e-9 w=widthn1 n=ngatesn1 c2gs=1e-6 c2gd=1.8e-6 m=1 mm=0 xm1 pad net15 pwrn pwrn NESDB_5V l=600e-9 w=widthm1 n=ngatesm1 c2gs=1e-6 c2gd=1.8e-6 m=1 mm=0 xd0 net15 pad pwrn DPD l=4e-6 w=10.5e-6 m=1 mm=0 xr1 net15 pwrn pwrn RWA l=29.8e-6 w=3.4e-6 m=1 mm=0 .ends ESDout_5V .subckt ESDPwrgnd_2X_5V pwrn pwrp xm0 pwrp net16 pwrn pwrn NESDBS_5V l=600e-9 w=420e-6 n=12 c2gs=1e-6 c2gd=3.8e-6 m=1 mm=0 xm1 pwrp net16 pwrn pwrn NESDBS_5V l=600e-9 w=420e-6 n=12 c2gs=1e-6 c2gd=3.8e-6 m=1 mm=0 xd0 net16 pwrp pwrn DPD l=4e-6 w=10.5e-6 m=1 mm=0 xr2 pwrn pwrn pwrn RWA l=11.1e-6 w=2.8e-6 m=1 mm=0 xr0 net16 net19 pwrn RWA l=11.1e-6 w=2.8e-6 m=1 mm=0 xr1 net19 pwrn pwrn RWA l=11.1e-6 w=2.8e-6 m=1 mm=0 .ends ESDPwrgnd_2X_5V .subckt GPAD in .ends GPAD .subckt FXWA9306Z_sp a0 a1 b0 b1 gnd oe vcca vccb r0 net055 gnd 1 r1 net071 gnd 1 r3 net073 gnd 1 r6 net037 gnd 1 r4 net069 gnd 1 r5 net039 gnd 1 r2 net065 gnd 1 xi28 gnd oe net34 vcca vccb biasiso xi17 oe net055 ESDIn_2X_5V xi19 a1 b1 gnd net34 SWI xi18 a0 b0 gnd net34 SWI xi20 b0 net065 ESDout_5V widthn1=210e-6 ngatesn1=6 widthm1=210e-6 ngatesm1=6 xi9 a1 net037 ESDout_5V widthn1=210e-6 ngatesn1=6 widthm1=210e-6 ngatesm1=6 xi21 b1 net069 ESDout_5V widthn1=210e-6 ngatesn1=6 widthm1=210e-6 ngatesm1=6 xi176 b0 net071 ESDout_5V widthn1=210e-6 ngatesn1=6 widthm1=210e-6 ngatesm1=6 xi169 b1 net073 ESDout_5V widthn1=210e-6 ngatesn1=6 widthm1=210e-6 ngatesm1=6 xi167 a0 net039 ESDout_5V widthn1=210e-6 ngatesn1=6 widthm1=210e-6 ngatesm1=6 xi25 gnd vccb ESDPwrgnd_2X_5V xi173 gnd vcca ESDPwrgnd_2X_5V xi175 gnd vccb ESDPwrgnd_2X_5V xi172 gnd vcca ESDPwrgnd_2X_5V xi122 a1 GPAD xi63 a0 GPAD xi73 oe GPAD xi120 vccb GPAD xi127 b0 GPAD xi123 gnd GPAD xi126 b1 GPAD xi62 vcca GPAD .ends FXWA9306Z_sp .SUBCKT FXWA9306f A0 A1 OE B0 B1 VCCEXT VCCB GNDEXT xi0 a0 a1 b0 b1 gndext oe vccext vccb FXWA9306Z_sp .ENDS FXWA9306f * .PROT freelib 5a2Z[7-u#/js;B-i:'%ep$v,C'/25B]+):fJ5H#uC(1y)e-u>9%J;X5i#'%s$B-,(2/e5BvwC'f:9H]uC:xJ5ejH>(%J)[ 8 q 5E2zV[ 8 Xr=$3W%