*Model File name : fsdusb11f
************************************************************************
* FAIRCHILD I/O SPICE DECK FOR fsdusb11
************************************************************************
*
* Model Name: fsdusb11
* Date Created/Updated :7/11/2005
* Revision Number: 1.0b
* Updated By: Julie Stultz
*
* Model Type: I/O Subcircuit
* Package models included: MICROPAK_10 TSSOP14
* Process: fast
* Verified on Avanti Star-HSPICE Version 2001.4
********************************************************************************
* DISCLAIMER:
********************************************************************************
*
* Fairchild Semiconductor Corporation hereby grants the user of this
* SPICE model a non-exclusive, nontransferable license to use this
* SPICE model under the following terms.  Before using this
* SPICE model, the user should read this license.
*
* The user is granted this license only to use the SPICE model and is
* not granted rights to sell, loan, rent, lease or license the SPICE
* model in whole or in part, or in modified form to anyone other than
* user. User may modify the SPICE model to suit its specific
* applications but rights to derivative works and such modifications
* shall belong to Fairchild.
*
* This SPICE model is provided on an "AS IS" basis and Fairchild Semiconductor
* makes absolutely no warranty with respect to the information contained
* herein.  FAIRCHILD DISCLAIMS AND CUSTOMER WAIVES ALL WARRANTIES,
* EXPRESS OR IMPLIED, INCLUDING WARRANTIES OF MERCHANTABILITY OR FITNESS
* FOR A PARTICULAR PURPOSE. The entire risk as to quality and performance
* is with the Customer.  ACCORDINGLY, IN NO EVENT SHALL THE COMPANY BE
* LIABLE FOR ANY DAMAGES, WHETHER IN CONTRACT OR TORT, INCLUDING ANY
* LOST PROFITS OR OTHER INCIDENTAL, CONSEQUENTIAL, EXEMPLARY, OR
* PUNITIVE DAMAGES ARISING OUT OF THE USE OR APPLICATION OF THE SPICE
* model provided in this package.  Further, Fairchild reserves the right
* to make changes without notice to any product herein to improve,
* reliability, function, or design.  Fairchild does not convey any license
* under patent rights or any other intellectual property rights,
* including those of third parties.
*
* Fairchild is not obligated to provide maintenance or support for
* the licensed SPICE model.
*
********************************************************************************
* SPECIAL NOTES:
********************************************************************************
*
*
* Beta HSPICE Model Disclaimer
*
* This HSPICE model is classified as a "Beta Model Only".  "Beta Models" have
* been verified for operation and functionality ONLY.  These models HAVE NOT
* been correlated to current processes or design characteristics.
* It is believed that these "Beta Models" were representative of the design
* and process at the time of their introduction though no level of accuracy
* is implied.
*
* All "Beta Models" are clearly marked "BETA MODEL ONLY".  "Beta Models" are
* used at your own risk and should be treated as an approximate representation
* of the silicon device.  There is no support available for "Beta Models".
* If you have questions or concern regarding this policy please contact your
* local sales representative, the Fairchild Semiconductor Technical Response
* Center (1-877-564-4263) or visit the Fairchild Semiconductor website at
* http://www.fairchildsemi.com
*
**                       All material contained herein is
*                  COPYRIGHT 2004 - Fairchild Semiconductor Corporation
*
*
*
********************************************************************************
*
* THIS MODEL MAY CONTAIN MODIFIED FUNCTIONALITY. IT MAY NOT REPRESENT TIMING
* CHARACTERISTICS OF THE fsdusb11 OR ANY OTHER FAIRCHILD SEMICONDUCTOR DEVICE.
* IT IS REPRESENTATIVE OF THE BASIC INPUT, OUTPUT CHARACTERISTICS OF THE
* fsdusb11 DEVICE.
*
* The terminals of this netlist are described as follows:
********************************************************************************
*
*
*	D1P	=	Switch Input
*	D1M	=	Switch Input
*	D2M	=	Switch Input
*	D2P	=	Switch Input
*	S1	=	Control Input
*	S2	=	Control Input
*	DP	=	P Common Port
*	DM	=	M Common Port
*	VCCEXT	=	Power Pin
*	GNDEXT	=	Ground Pin
*
*
*
* Spice Subcircuits for Package Pins
*
************************************************************************************
*
* These files are subcircuit spice models for the Fairchild Semiconductor
* logic devices. They are intended for use as package models
* which will accurately represent the characteristics of the
* indicated package pins.
*
* These model files can be used independently from temperature.
*
* The terminals of these subcircuits are labelled as follows:
*       EXT         node    1
*       I           node    3
*       GNDI        node    GND
*
* SPECIAL NOTES:
*   1. The EXT node is the node which is used to connect external loads
*      to the package.  The INT node is the node which is used to connect
*      input or output subcircuits to the package elements.  In other
*      words, this is the bond pad node.
*   2. The GNDI node is a ground node which is internal to a package.  All
*      subcircuits which represent internal circuits in a package should
*      have their GNDI nodes connected together.  The GNDI node should NOT
*      be connected to a ground reference node which is used with
*      external voltage generators.
*   3. The inductors which are labelled as L$2 represent average bond
*      wire inductances.  They are not part of the inductance matrix for
*      the package lead fingers.
*
***********************************************************************************
* PACKAGES
*
***********************************************************************
*   10 PIN uPak PACKAGE - CORNER PIN
***********************************************************************
.SUBCKT microCRNR 1 3 GND
R$1 1 2 0.011
R$2 2 3 10000000
L$1 2 4 0.05NH
L$2 4 3 0.15NH
C$1 3 GND 0.08PF
.ENDS
*
***********************************************************************
*   10 PIN uPak PACKAGE - CENTER PIN
***********************************************************************
.SUBCKT microMID 1 3 GND
R$1 1 2 0.02
R$2 2 3 10000000
L$1 2 4 0.07NH
L$2 4 3 0.23NH
C$1 3 GND 0.08PF
.ENDS
*
***********************************************************************
*   14 PIN TSSOP PACKAGE - CORNER PIN
***********************************************************************
.SUBCKT TSSOP14CRNR 1 3 GND
R$1 1 2 0.10
R$2 2 3 10000000
L$1 2 4 2.50NH
L$2 4 3 0.50NH
C$1 3 GND 0.22PF
.ENDS
*
***********************************************************************
*   14 PIN TSSOP PACKAGE - CENTER PIN
***********************************************************************
.SUBCKT TSSOP14MID 1 3 GND
R$1 1 2 0.08
R$2 2 3 10000000
L$1 2 4 1.50NH
L$2 4 3 0.50NH
C$1 3 GND 0.10PF
.ENDS
*
***********************************************************************
* END OF PACKAGES
***********************************************************************
*
***********************************************************************
* TEST FORCING FUNCTIONS
* (Uncomment the following to test including .END)
***********************************************************************
*
*VPWR0 VCCEXT GNDEXT 5.0
*VDATA0 D1P GNDEXT DC 0
*VDATA1 D1M GNDEXT DC 0
*VDATA2 D2M GNDEXT DC 5.0
*VDATA3 D2P GNDEXT DC 5.0
*VENB0 S1 GNDEXT PULSE 5.0 0.0 15E-9 2.0E-9 2.0E-9 47.5E-9 100E-9
*VENB1 S2 GNDEXT PULSE 0.0 5.0  15E-9 2.0E-9 2.0E-9 47.5E-9 100E-9
*VGND0 GNDEXT 0  DC  0
*
*********************************************************************
* LOAD
*********************************************************************
*R0 DP GNDEXT 50
*C0 DP GNDEXT 35p
*R1 DM GNDEXT 50
*C1 DM GNDEXT 35p
**********************************************************************
* OPTIONS
**********************************************************************
*
*.temp = -40
*.OPTION  INGOLD=2 ARTIST=2 PSF=2 post=2
*+        PROBE=0
*+        GMINDC = 1.00000E-12
*+        GMIN   = 1.00000E-12
*+        method = gear LVLTIM = 2 chgtol = 1e-9
*.plot V(D1P) V(D1M) V(D2M) V(D2P) V(S1) V(S2) V(DP) V(DM)
*.tran 1.0ns 200ns
*
*************************************************************************
* END OF TEST FORCING FUNCTIONS
*************************************************************************
*
***********************************************************************
* XDIE is the top call for the subckt for the die only (no package model)
* XPKG is the top call for the subckt for slice with package model
*
* Uncomment Top call desired
***********************************************************************
*
* XDIE  D1P D1M D2M D2P S1 S2 DP DM VCCEXT GNDEXT fsdusb11f
*
*
*************************************************************************
* PACKAGE CALL
*************************************************************************
*
*XPKG  D1P D1M D2M D2P S1 S2 DP DM VCCEXT GNDEXT fsdusb11fl10
.SUBCKT fsdusb11fl10 D1P D1M D2M D2P S1 S2 DP DM VCCEXT GNDEXT
X0 D1P D1PI GNDEXT MICROCRNR
X1 D1M D1MI GNDEXT MICROCRNR
X2 D2M D2MI GNDEXT MICROCRNR
X3 D2P D2PI GNDEXT MICROCRNR
X4 S1 S1I GNDEXT MICROMID
X5 S2 S2I GNDEXT MICROMID
X6 DP DPI GNDEXT MICROMID
X7 DM DMI GNDEXT MICROMID
X8 VCCEXT VCCEXTI GNDEXT MICROMID
X9 GNDEXT GNDEXTI GNDEXT MICROMID
X10 D1PI D1MI D2MI D2PI S1I S2I DPI DMI VCCEXTI GNDEXTI fsdusb11f
.ENDS fsdusb11fl10
*
*
*XPKG  D1P D1M D2M D2P S1 S2 DP DM VCCEXT GNDEXT fsdusb11fmt
.SUBCKT fsdusb11fmt D1P D1M D2M D2P S1 S2 DP DM VCCEXT GNDEXT
X0 D1P D1PI GNDEXT TSSOP14CRNR 
X1 D1M D1MI GNDEXT TSSOP14CRNR 
X2 D2M D2MI GNDEXT TSSOP14CRNR 
X3 D2P D2PI GNDEXT TSSOP14CRNR 
X4 S1 S1I GNDEXT TSSOP14MID
X5 S2 S2I GNDEXT TSSOP14MID
X6 DP DPI GNDEXT TSSOP14MID
X7 DM DMI GNDEXT TSSOP14MID
X8 VCCEXT VCCEXTI GNDEXT TSSOP14MID
X9 GNDEXT GNDEXTI GNDEXT TSSOP14MID
X10 D1PI D1MI D2MI D2PI S1I S2I DPI DMI VCCEXTI GNDEXTI fsdusb11f
.ENDS fsdusb11fmt
*************************************************************************
*
.SUBCKT fsdusb11f  D1P D1M D2M D2P S1 S2 DP DM VCCEXT GNDEXT
XI0 D1M D1P D2M D2P DM DP GNDEXT S1 S2 VCCEXT FSDUSB11_G14
.ENDS fsdusb11f
*
.prot FREELIB
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