***********************************************************************
* FAIRCHILD SPICE DECK FOR FST 16211
***********************************************************************
*
* MODEL NAME: 16211F.SIO
* DATE CREATED/UPDATED: CREATED 11/98
* REVISION NUMBER: 2.0 (BULK RESISTANCE ADDED)
* DESIGNERS INITIALS: M MISKE, PRL
*
* MODEL TYPE: SINGLE BIT,  PACKAGE MODEL INCLUDED (TSSOP-56)
* PROCESS TYPE: FAST
* TEMP RANGE: -55C TO +125C
*
* VERIFIED ON AVANTI STAR-HSPICE VERSION 97.4
*
********************************************************************************
*
* FAIRCHILD SEMICONDUCTOR CORPORATION HEREBY GRANTS THE USER OF THIS
* SPICE MODEL A NON-EXCLUSIVE, NONTRANSFERABLE LICENSE TO USE THIS
* SPICE MODEL UNDER THE FOLLOWING TERMS.  BEFORE USING THIS
* SPICE MODEL, THE USER SHOULD READ THIS LICENSE.
*
* THE USER IS GRANTED THIS LICENSE ONLY TO USE THE SPICE MODEL AND IS
* NOT GRANTED RIGHTS TO SELL, LOAD, RENT, LEASE OR LICENSE THE SPICE
* MODEL IN WHOLE OR IN PART, OR IN MODIFIED FORM TO ANYONE OTHER THAN
* USER. USER MAY MODIFY THE SPICE MODEL TO SUIT ITS SPECIFIC
* APPLICATIONS BUT RIGHTS TO DERIVATIVE WORKS AND SUCH MODIFICATIONS
* SHALL BELONG TO FAIRCHILD.
*
* THIS SPICE MODEL IS PROVIDED ON AN 'AS IS' BASIS AND FAIRCHILD SEMICONDUCTOR
* MAKES ABSOLUTELY NO WARRANTY WITH RESPECT TO THE INFORMATION CONTAINED
* HEREIN.  FAIRCHILD DISCLAIMS AND CUSTOMER WAIVES ALL WARRANTIES,
* EXPRESS OR IMPLIED, INCLUDING WARRANTIES OF MERCHANTABILITY OR FITNESS
* FOR A PARTICULAR PURPOSE. THE ENTIRE RISK AS TO QUALITY AND PERFORMANCE
* IS WITH THE CUSTOMER.  ACCORDINGLY, IN NO EVENT SHALL THE COMPANY BE
* LIABLE FOR ANY DAMAGES, WHETHER IN CONTRACT OR TORT, INCLUDING ANY
* LOST PROFITS OR OTHER INCIDENTAL, CONSEQUENTIAL, EXEMPLARY, OR
* PUNITIVE DAMAGES ARISING OUT OF THE USE OR APPLICATION OF THE SPICE
* MODEL PROVIDED IN THIS PACKAGE.  FURTHER, FAIRCHILD RESERVES THE RIGHT
* TO MAKE CHANGES WITHOUT NOTICE TO ANY PRODUCT HEREIN TO IMPROVE,
* RELIABILITY, FUNCTION, OR DESIGN.  FAIRCHILD DOES NOT CONVEY ANY LICENSE
* UNDER PATENT RIGHTS OR ANY OTHER INTELLECTUAL PROPERTY RIGHTS,
* INCLUDING THOSE OF THIRD PARTIES.
*
* FAIRCHILD IS NOT OBLIGATED TO PROVIDE MAINTENANCE OR SUPPORT FOR
* THE LICENSED SPICE MODEL.
*
*
********************************************************************************
* SPECIAL NOTES:
********************************************************************************
*
*      THE SPICE INPUT FILES CONTAINED ON  THIS  DISK  ARE
*      BELIEVED  TO BE  VALID REPRESENTATIONS OF THE INPUT, OUTPUT,  I/O  AND
*      ASSOCIATED  CIRCUITRY  USED ON THE LOGIC DEVICE  MODELED.  THESE
*      SPICE  SIMULATION INPUT  FILES ARE INTENDED TO BE A USEFUL AND
*      BENEFICIAL TOOL TO THE  SYSTEM DESIGNER  FOR  THE  PURPOSE OF MODELING
*      BUS  LOADING  AND CERTAIN  DRIVE CHARACTERISTICS. HOWEVER, DUE TO THE
*      COMPLEXITIES INDIGENOUS TO THE MODELING OF TRANSIENT PHENOMENON,
*      FAIRCHILD  SEMICONDUCTOR  RECOMMENDS  THAT SIMULATED RESULTS BE
*      SUPPORTED BY LABORATORY  CHARACTERIZATION  PRIOR TO MAKING FINAL
*      JUDGMENTS REGARDING DEVICE TRANSIENT PERFORMANCE. FSC STRONGLY
*      RECOMMENDS THAT SPICE SIMULATION NOT BE USED IN PLACE OF ACTUAL DEVICE
*      CHARACTERIZATION.
*
*
*                       ALL MATERIAL CONTAINED ON THIS DISK IS
*                  COPYRIGHT 1998 - FAIRCHILD SEMICONDUCTOR CORPORATION
*
*
*
* CONTACT FAIRCHILD AT ATTN: LOGIC APPLICATIONS/SPICE MODELS.
* FAIRCHILD SEMICONDUCTOR, M/S 10-26 333 WESTERN AVENUE, S. PORTLAND,
* MAINE 04106 OR FAIRCHILD'S TECHNICAL RESPONSE GROUP AT 888-522-5372.
*
*               WWW.FAIRCHILDSEMI.COM
*
********************************************************************************
*
*  NODES/PINOUTS:
********************************************************************************
* A1 = A-SIDE I/O
* B1 = B-SIDE I/O
* OE = OUTPUT ENABLE
* VCC = POWER PIN
* GND = GROUND
*
* SUBCIRCUIT CALL = FST16211
*********************************************************************
* FULL PATH CONNECTION INPUT TO OUTPUT
***********************************************************************
.SUBCKT FST16211FMT A1 B1 OE VCC GND
X1 A1 A1_1 GND TSSOP56MID
X2 B1 B1_1 GND TSSOP56MID
X3 OE OE1 GND TSSOP56CRNR
X4 VCC PWRP GND TSSOP56MID
X6 GND PWRN GND TSSOP56MID
X7 A1_1 B1_1 OE1 PWRP PWRN SLICE
.ENDS FST16211FMT
*************************************************************************
* PACKAGE SUBCIRCUITS
**************************************************************************
.SUBCKT TSSOP56CRNR 1 3 GND
R$1 1 2 0.15
R$2 2 3 10000000
L$1 2 4 3.66NH
L$2 4 3 0.69NH
C$1 3 GND 0.32PF
.ENDS
.SUBCKT TSSOP56MID 1 3 GND
R$1 1 2 0.10
R$2 2 3 10000000
L$1 2 4 0.72NH
L$2 4 3 0.65NH
C$1 3 GND 0.10PF
.ENDS
********************************************************************************
*
*  NETLIST
********************************************************************************
.prot FREELIB
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