*Model File name : fan156zs
********************************************************************************
* FAIRCHILD I/O SPICE DECK FOR fan156z
********************************************************************************
*
* Model Name: fan156z
* Date Created/Updated :06/19/2014
* Revision Number: 1.0
* Created By: W0012571
*
* Model Type: I/O Subcircuit
* Package models included: MICROPAK_6 
* Process: Slow
* Verified on HSPICE Version D-2010.03 32-BIT
********************************************************************************
* DISCLAIMER:
********************************************************************************
*
* Fairchild Semiconductor Corporation hereby grants the user of this
* SPICE model a non-exclusive, nontransferable license to use this
* SPICE model under the following terms.  Before using this
* SPICE model, the user should read this license.
*
* The user is granted this license only to use the SPICE model and is
* not granted rights to sell, loan, rent, lease or license the SPICE
* model in whole or in part, or in modified form to anyone other than
* user. User may modify the SPICE model to suit its specific
* applications but rights to derivative works and such modifications
* shall belong to Fairchild.
*
* This SPICE model is provided on an "AS IS" basis and Fairchild Semiconductor
* makes absolutely no warranty with respect to the information contained
* herein.  FAIRCHILD DISCLAIMS AND CUSTOMER WAIVES ALL WARRANTIES,
* EXPRESS OR IMPLIED, INCLUDING WARRANTIES OF MERCHANTABILITY OR FITNESS
* FOR A PARTICULAR PURPOSE. The entire risk as to quality and performance
* is with the Customer.  ACCORDINGLY, IN NO EVENT SHALL THE COMPANY BE
* LIABLE FOR ANY DAMAGES, WHETHER IN CONTRACT OR TORT, INCLUDING ANY
* LOST PROFITS OR OTHER INCIDENTAL, CONSEQUENTIAL, EXEMPLARY, OR
* PUNITIVE DAMAGES ARISING OUT OF THE USE OR APPLICATION OF THE SPICE
* model provided in this package.  Further, Fairchild reserves the right
* to make changes without notice to any product herein to improve,
* reliability, function, or design.  Fairchild does not convey any license
* under patent rights or any other intellectual property rights,
* including those of third parties.
*
* Fairchild is not obligated to provide maintenance or support for
* the licensed SPICE model.
*
********************************************************************************
* SPECIAL NOTES:
********************************************************************************
*
*
* Beta HSPICE Model Disclaimer
*
* This HSPICE model is classified as a "Beta Model Only".  "Beta Models" have
* been verified for operation and functionality ONLY.  These models HAVE NOT
* been correlated to current processes or design characteristics.
* It is believed that these "Beta Models" were representative of the design
* and process at the time of their introduction though no level of accuracy
* is implied.
*
* All "Beta Models" are clearly marked "BETA MODEL ONLY".  "Beta Models" are
* used at your own risk and should be treated as an approximate representation
* of the silicon device.  There is no support available for "Beta Models".
* If you have questions or concern regarding this policy please contact your
* local sales representative, the Fairchild Semiconductor Technical Response
* Center (1-877-564-4263) or visit the Fairchild Semiconductor website at
* http://www.fairchildsemi.com
*
**             All material contained herein is
*          COPYRIGHT 2014 - Fairchild Semiconductor Corporation
*
*
*
********************************************************************************
*
* THIS MODEL MAY CONTAIN MODIFIED FUNCTIONALITY. IT MAY NOT REPRESENT TIMING
* CHARACTERISTICS OF THE fan156z OR ANY OTHER FAIRCHILD SEMICONDUCTOR DEVICE.
* IT IS REPRESENTATIVE OF THE BASIC INPUT, OUTPUT CHARACTERISTICS OF THE
* fan156z DEVICE.
*
* The terminals of this netlist are described as follows:
********************************************************************************
*
*
*         INP = Non-inverting input of Comparator
*         INN = Inverting input of Comparator
*         OUT = Comparator output
*         OUT = Power Pin
*         OUT = Ground Pin
*
*
*
* Spice Subcircuits for Package Pins
*
********************************************************************************
*
* These files are subcircuit spice models for the Fairchild Semiconductor
* logic devices. They are intended for use as package models 
* which will accurately represent the characteristics of the
* indicated package pins.
*
* These model files can be used independently from temperature.
*
* The terminals of these subcircuits are labelled as follows:
*     EXT     node  1
*     I       node  3
*     GNDI    node  GND
*
* SPECIAL NOTES:
*   1. The EXT node is the node which is used to connect external loads
*    to the package.  The INT node is the node which is used to connect
*    input or output subcircuits to the package elements.  In other
*    words, this is the bond pad node.
*   2. The GNDI node is a ground node which is internal to a package.  All
*    subcircuits which represent internal circuits in a package should
*    have their GNDI nodes connected together.  The GNDI node should NOT
*    be connected to a ground reference node which is used with
*    external voltage generators.
*   3. The inductors which are labelled as L$2 represent average bond
*    wire inductances.  They are not part of the inductance matrix for
*    the package lead fingers.
*
********************************************************************************
* PACKAGES 
*
***********************************************************************
*   micropak PACKAGE - CORNER PIN
***********************************************************************
.SUBCKT microCRNR 1 3 GND
 R$1 1 2 0.049
 R$2 2 3 10000000
 L$1 2 4 0.32NH
 L$2 4 3 0.45NH
 C$1 3 GND 0.17PF
.ENDS
*
***********************************************************************
*   micropak PACKAGE - CENTER PIN
***********************************************************************
.SUBCKT microMID 1 3 GND
 R$1 1 2 0.049
 R$2 2 3 10000000
 L$1 2 4 0.41NH
 L$2 4 3 0.19NH
 C$1 3 GND 0.07PF
.ENDS
*
********************************************************************************
* END OF PACKAGES 
********************************************************************************
*
********************************************************************************
* TEST FORCING FUNCTIONS
* (Uncomment the following to test including .END)
********************************************************************************
*
*VPWR0 VCCEXT GNDEXT 3
*VDATA0 INP GNDEXT DC 0
*VDATA1 INN GNDEXT DC 0
*VGND0 GNDEXT 0  DC  0 
*
********************************************************************************
* LOAD 
********************************************************************************
*R0 OUT GNDEXT 1000000000 
*C0 OUT GNDEXT 15p 
********************************************************************************
* OPTIONS 
********************************************************************************
*
*.temp = 85
*.OPTION  INGOLD=2 ARTIST=2 PSF=2 post=2
*+      PROBE=0 
*+      GMINDC = 1.00000E-12
*+      GMIN   = 1.00000E-12
*+      method = gear LVLTIM = 2 chgtol = 1e-9
*.plot V(INP) V(INN) V(OUT)*
********************************************************************************
* END OF TEST FORCING FUNCTIONS 
********************************************************************************
*
********************************************************************************
* XDIE is the top call for the subckt for the die only (no package model) 
* XPKG is the top call for the subckt for slice with package model 
*
* Uncomment Top call desired 
********************************************************************************
* 
*XDIE  INP INN OUT VCCEXT GNDEXT fan156zsdi
*
*
********************************************************************************
* PACKAGE CALL 
********************************************************************************
*
*XPKG  INP INN OUT VCCEXT GNDEXT fan156zsl6

.SUBCKT fan156zsl6 INP INN OUT VCCEXT GNDEXT
X0 INP INPI GNDEXT MICROCRNR 
X1 INN INNI GNDEXT MICROCRNR 
X2 OUT OUTI GNDEXT MICROCRNR 
X3 VCCEXT VCCEXTI GNDEXT MICROCRNR 
X4 GNDEXT GNDEXTI GNDEXT MICROMID 
X5 INPI INNI OUTI VCCEXTI GNDEXTI fan156zsdi
.ENDS fan156zsl6
* 
********************************************************************************
*
* All included files
* All included files
.INCLUDE "./fan156z_init.txt"

* All libraries
.lib "./fan156z_lib.txt" ss

*
.SUBCKT fan156zsdi  INP INN OUT VCCEXT GNDEXT
 xi0 inn inp out vccext gndext fan156z_top
.ENDS fan156zsdi
*
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