1:8 HCSL Fanout Buffer Evaluation Board

Overview

The NB3L208KMNGEVB evaluation board is designed to test and evaluate the NB3L208K, which is a differential 1:8 Clock fanout buffer with High-speed Current Steering Logic (HCSL) outputs. Inputs can directly accept differential LVPECL, LVDS and HCSL signals. Single-ended LVPECL, HCSL, LVCMOS, or LVTTL levels are accepted with a proper external VTH reference supply. These signals will be translated to HCSL and eight identical copies of Clock will be distributed, operating up to 350 MHz.

Evaluation/Development Tools

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1:8 HCSL Fanout Buffer Evaluation Board

Evaluation Board

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Technical Documentation

Name / Description

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Modified date

EVBUM2295/D

1

Eval Board: Manual

434.18 KB

EN

Eval Board: Manual

December 01, 2019

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