Evaluation Board | NB3L202KMNGEVB

The NB3L202KMNGEVB is designed to effectively evaluate the NB3L202K, which is a differential 1:2 Clock fanout buffer with High−speed Current Steering Logic (HCSL) outputs. Inputs can directly accept differential LVPECL, LVDS, and HCSL signals. Single−ended LVPECL, HCSL, LVCMOS, or LVTTL levels are accepted with a proper external Vth reference supply per Figures 4 and 6. The input signal will be translated to HCSL and provides two identical copies operating up to 350 MHz. The NB3L202K is optimized for ultra−low phase noise, propagation delay variation and low output–to–output skew, and is DB200H compliant. As such, system designers can take advantage of the NB3L202K’s performance to distribute low skew clocks across the backplane or the motherboard making it ideal for Clock and Data distribution applications such as PCI Express, FBDIMM, Networking, Mobile Computing, Gigabit Ethernet, etc. Output drive current is set by connecting a 475  resistor from IREF (Pin 10) to GND per Figure 11. Outputs can also interface to LVDS receivers when terminated per Figure 12.