Chipset Sensitivity

nMOS Innovations in CMOS Technology

Change Reason for Implementation Impact on ESD
Shallower Junctions Allows Shorter Channel Length Transistors Higher Current Density During an ESD Event
Lightly Doped Drains Reduce Hot Carrier Transistor Degradation Degraded Performance of Parasitic Bipolar Transistor which Provides Intrinsic High Current Capability
Silicided Junctions Reduced Transistor Series Resistance Removes Ballast Resistance in nMOS Drains, Degrading High Current Carrying Capability of Parasitic Bipolar Transistor
Thin Gate Oxides Improved Transistor Performance Reduced Voltage at Which Oxide Damage Occurs

Operating voltage for advanced ICs from the International Technology Roadmap for Semiconductors - Graph

*Operating voltage for advanced ICs from the International Technology Roadmap for Semiconductors.

 

Why External ESD Protection is Needed

Why External ESD Protection is Needed - Graph

*Image taken from ESD Association White Paper II, "Trends in Semiconductor Technology and ESD Testing", © ESDA

Trend: Chipsets geometries reduced to support faster data rates
Result: Chipsets becoming more sensitive to ESD voltage - Oxide Vbr decreasing

For more information please refer to ON Semiconductor Application Note, Trends in Integrated Circuits that Affect ESD Protection Requirements

 

Clamping Voltage Requirements vs. Performance

Clamping Voltage Requirements vs. Performance - Graph

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