Clock / Data Fanout Buffer, 1:10 Differential, 3.3 V, with HCSL Outputs

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Overview

The NB3N111K is a differential 1 to 10 Clock and Data fanout buffer with Highspeed Current Steering Logic (HCSL) outputs optimized for ultra low propagation delay variation. The NB3N111K is designed with HCSL clock distribution and FBDIMM applications in mind.

  • Clock Distribution
  • PCIe I, II, II
  • Networking
  • High End Computing
  • Servers
  • Routers
  • FBDIMM Memory Card
  • Typical Input Clock Frequency 100, 133, 166, or 400 MHz
  • 220 ps Typical Rise and Fall Times
  • 800 ps Typical Propagation Delay
  • Delta tpd 100 ps Maximum Propagation Delay Variation per Diff Pair
  • 0.1 ps Typical RMS Phase Jitter
  • Operating Range: VCC = 3.0 V to 3.6 V with GND = 0 V
  • Differential HCSL Output Levels

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Status

CAD Models

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Package Type

Case Outline

MSL Type

MSL Temp (°C)

Container Type

Container Qty.

ON Target

Type

Channels

Input / Output Ratio

Input Level

Output Level

VCC Typ (V)

tJitterRMS Typ (ps)

tskew(o-o) Max (ps)

tpd Typ (ns)

tR & tF Max (ps)

fmaxClock Typ (MHz)

fmaxData Typ (Mbps)

Reference Price

NB3N111KMNR4G

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Active

CAD Model

Pb

A

H

P

QFN-32

1

260

REEL

1000

Y

Buffer

1

1:10

TTL

HCSL

3.3

0.1

100

0.8

400

400

400

Price N/A

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