Product Description
High-Performance Silicon-Gate CMOS
The MC74HC4046A is similar in function to the MC14046 Metal gate CMOS device. The device inputs are compatible with standard CMOS outputs; with pullup resistors, they are compatible with LSTTL outputs.
The HC4046A phase-locked loop contains three phase comparators, a voltage-controlled oscillator (VCO) and unity gain op-amp DEM
OUT. The comparators have two common signal inputs, COMP
IN, and SIG
IN. Input SIG
IN and COMP
IN can be used directly coupled to large voltage signals, or indirectly coupled (with a series capacitor to small voltage signals). The self-bias circuit adjusts small voltage signals in the linear region of the amplifier. Phase comparator 1 (an exclusive OR gate) provides a digital error signal PC1
OUT and maintains 90 degrees phase shift at the center frequency between SIG
IN and COMP
IN signals (both at 50% duty cycle). Phase comparator 2 (with leading-edge sensing logic) provides digital error signals PC2
OUT and PCP
OUT and maintains a 0 degree phase shift between SIG
IN and COMP
IN signals (duty cycle is immaterial). The linear VCO produces an output signal VCO
OUT whose frequency is determined by the voltage of input VCO
IN signal and the capacitor and resistors connected to pins C1A, C1B, R1 and R2. The unity gain op-amp output DEM
OUT with an external resistor is used where the VCO
IN signal is needed but no loading can be tolerated. The inhibit input, when high, disables the VCO and all op-amps to minimize standby power consumption.
Applications include FM and FSK modulation and demodulation, frequency synthesis and multiplication, frequency discrimination, tone decoding, data synchronization and conditioning, voltage-to-frequency conversion and motor speed control.
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Features |
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Output Drive Capability: 10 LSTTL Loads
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Low Power Consumption Characteristic of CMOS Devices
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Operating Speeds Similar to LSTTL
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Wide Operating Voltage Range: 3.0 to 6.0 V
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Low Input Current: 1.0 mA Maximum (except SIGIN and COMPIN)
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In Compliance with the Requirements Defined by JEDEC Standard No. 7A
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Low Quiescent Current: 80 mA Maximum (VCO disabled)
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High Noise Immunity Characteristic of CMOS Devices
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Diode Protection on all Inputs
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Chip Complexity: 279 FETs or 70 Equivalent Gates
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