| Product Description |
The ONC18 process from ON Semiconductor is a low cost industry compatible 0.18 µm CMOS technology manufactured in the United States. This full featured process includes 1.8 V/3.3 V dual gate I/Os, nominal and high value MIM capacitors, resistors, and six levels of metal. A comprehensive design kit offers an expansive core, I/O, and memory library. Specialty services including stitching and shuttle prototyping are available. ONC18 also serves as a platform for highly integrated high voltage mixed-signal processes ideal for many automotive, industrial, medical, and military applications.
|
| Features |
- 4 to 6 Metal layers
- 1.0 fF/µm2 Metal-insulator-metal (MIM) capacitor
- 2.0 fF/µm2 Metal-insulator-metal (MIM) capacitors (design dependent)
- Salicide process with optional blocking
- 1.8 V core voltage with 3.3 V I/O voltage
- Poly, diffusion, and well resistors
Process Characteristics
| Operating Voltage |
1.8 V, 3.3 V |
| Substrate Material |
P-Type |
| Drawn Transistor Length |
0.18 µm |
| Gate Oxide Thickness |
2.9 nm/6.5 nm |
| Contact/Via Size |
0.22 µm/0.26 µm/0.28 µm (Via 5) |
| Metal Thickness |
M1-5 - 0.56 µm
M6 - 0.94 µm |
| Contacted Metal Pitch |
| Metal 1 |
0.46 µm |
| Metal 2-5 |
0.56 µm |
| Metal 6 |
1.0 µm |
| Metal 7 (RDL) |
5.0 µm |
| Metal Composition |
AI/TiN |
Sample Process Options
| |
Mask Layers |
| 1 poly, 4 metal |
24 |
| 1 poly, 5 metal |
26 |
| 1 poly, 6 metal |
28 |
| 1 poly, 4 metal, MIM |
25 |
| 1 poly, 5 metal, MIM |
27 |
| 1 poly, 6 metal, MIM |
29 |
|
| Device Characteristics |
|
(All Values Typical at 25°C)
Transistors
| N-Channel |
Typical Value |
Unit |
| Vt |
0.42 |
V |
| Idsat |
600 |
µA/µm |
| P-Channel |
Typical Value |
Unit |
| Vt |
-0.50 |
V |
| Idsat |
-260 |
µA/µm |
Thick Gate Transistors
| N-Channel |
Typical Value |
Unit |
| Vt |
0.72 |
V |
| Idsat |
600 |
µA/µm |
| P-Channel |
Typical Value |
Unit |
| Vt |
-0.73 |
V |
| Idsat |
-300 |
µA/µm |
|
Resistors
| |
Typical Value |
Unit |
| N+ Poly |
4.0 |
Ω/square |
| P+ Poly |
4.0 |
Ω/square |
| N-Diffusion |
4.5 |
Ω/square |
| P-Diffusion |
4.5 |
Ω/square |
| N+ Poly Unsalicided |
290 |
Ω/square |
| P+ Poly Unsalicided |
330 |
Ω/square |
| N-Diffusion Unsalicided |
60 |
Ω/square |
| P-Diffusion Unsalicided |
130 |
Ω/square |
| N-Well |
900 |
Ω/square |
Capacitors
| |
Typical Value |
Unit |
| Area |
1.0 |
fF/µm2 |
|
|
| Libraries |
(All values typical at 1.8 V, 25°C)
| Front-End Digital Design |
| Digital |
| Synthesis Libraries |
| Simulation Libraries |
| Analog |
| Design Rules |
| Spice Models |
| Standard Cell |
| High Density Core Cell |
| 129 k gates/mm2 |
| 46 µW/MHz/gate |
| 120 ps gate delay (2 Input NAND, fanout = 2) |
| Mixed-Signal Core Cell |
| 120 k gates/mm2 |
| 28 µW/MHz/gate |
| 120 ps gate delay (2 Input NAND, fanout = 2) |
| I/O Library (core limited) |
| 70 µm in-line pad pitch |
| 40 µm staggered pad pitch |
| 40x235 µm cell (without pad) |
* Cadence IC 4.4.6 Compatible
|
| Memory Options |
| SRAM |
| Synchronous Single Port SRAM* |
| 150 kb/mm2 (64 K bit memory) |
| Synchronous Dual Port SRAM* |
| 75 kb/mm2 (64 K bit memory) |
| VIA-Programmable ROM* |
| 740 kb/mm2 (64 K bit memory) |
* Compiled
|
| CAD Tool Compatibility |
| Digital Design |
| Synopsys Design Compiler |
| Cadence RTL Compiler |
| Mentor Graphics FastScan (DFT) |
| Analog/Mixed Signal Design |
| Cadence Virtuoso, VirtuosoXL, Spectre |
| Mentor Graphics Design Architect IC, IC Station, and Eldo |
| Place and Route |
| Cadence Encounter |
| Physical Verification |
| Mentor Graphics Calibre |
|
| For more information please contact your local sales support at www.onsemi.com |
