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AN9093 MSOFET switch
I have been reading AN9093 and I think it is an excellent article for MOSFET switches.
For PMOS switch (Figure 7), although we see in the AN that R1,R2 and C1 is used, for
• R1 and R2 to set VGS.
• C1 to tune inrush current
Based on the content of the AN, C1 “dominates over CGD”, so C1 overrides CGD and successfully controls inrush current for CLOAD.
But for the gate driver Q1, the lack of corresponding additional “C1” means only very small parasitic capacitance CG2D2 exists, and does this suggest the plateau period should be extremely short, leading to ultrafast rise/fall time?
Also, since R1+R2 limits current, so there should be no necessity to consider any “inrush current”, which justifies the lack of corresponding “C1” between source and drain. Does this make sense?
So can we completely ignore the primary upper PMOS’s tuning circuit {R1,R2,C1}, for the gate driver Q1? Does Q1 affect rise/fall speed of the driver in any way?
The drive circuit of the NMOS should be independent of R1, R2, C1. The NMOS gate turn-on and turn-off will be determined by the gate drive circuit and the switching capabilities of the NMOS. R1, R2 will reduce the amount current that flows through the NMOS drain-to-source.
Answered by: ON Semiconductor
2015-01-19 09:48:17.296