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Hello, what device is recommended to protect todays FPGA I/O pins from overshoots and undershoots? Application: FPGA I/O bank supply 3.3V. Tolerated range is -0.5V ... +3.95V. Plan is: Card I/O (TTL/CMOS levels) <> ESD protection <> FET Bus-Switch (5V to 3.3V translation) <> Over/Under Protection Diodes <> FPGA I/O pin. Preferably 4 to 8 lines protection per device. Thank you.

You can look at the CM1230 for 2. 4, and 8 channel ESD protection. Please see the link for the datasheet at: http://www.onsemi.com/pub_link/Collateral/CM1230-D.PDF .Thank you. Answered by:
ON Semiconductor
2013-02-13 11:18:49.529