*********************************************************************** * FAIRCHILD I/O SPICE DECK FOR LCX573 ********************************************************************** * * MODEL NAME: LCX573T.SIO * DATE CREATED/UPDATED: 12/98 * REVISION NUMBER: 3.2 (BENCH CORRELATED, BULK RESISTANCE ADDED) * DESIGNERS INITIALS: PRL * ENCRYPTED BY APT * MODEL TYPE: I/O SUBCIRCUIT, PACKAGE MODEL INCLUDED (SOIC-20) * PROCESS TYPE: NOMINAL * TEMP RANGE:25C TO 150C * * VERIFIED ON AVANTI STAR-HSPICE VERSION 97.1 * ******************************************************************************** * DISCLAIMER: ******************************************************************************** * * FAIRCHILD SEMICONDUCTOR CORPORATION HEREBY GRANTS THE USER OF THIS * SPICE MODEL A NON-EXCLUSIVE, NONTRANSFERABLE LICENSE TO USE THIS * SPICE MODEL UNDER THE FOLLOWING TERMS. BEFORE USING THIS * SPICE MODEL, THE USER SHOULD READ THIS LICENSE. * * THE USER IS GRANTED THIS LICENSE ONLY TO USE THE SPICE MODEL AND IS * NOT GRANTED RIGHTS TO SELL, LOAN, RENT, LEASE OR LICENSE THE SPICE * MODEL IN WHOLE OR IN PART, OR IN MODIFIED FORM TO ANYONE OTHER THAN * USER. USER MAY MODIFY THE SPICE MODEL TO SUIT ITS SPECIFIC * APPLICATIONS BUT RIGHTS TO DERIVATIVE WORKS AND SUCH MODIFICATIONS * SHALL BELONG TO FAIRCHILD. * * THIS SPICE MODEL IS PROVIDED ON AN 'AS IS' BASIS AND FAIRCHILD SEMICONDUCTOR * MAKES ABSOLUTELY NO WARRANTY WITH RESPECT TO THE INFORMATION CONTAINED * HEREIN. FAIRCHILD DISCLAIMS AND CUSTOMER WAIVES ALL WARRANTIES, * EXPRESS OR IMPLIED, INCLUDING WARRANTIES OF MERCHANTABILITY OR FITNESS * FOR A PARTICULAR PURPOSE. THE ENTIRE RISK AS TO QUALITY AND PERFORMANCE * IS WITH THE CUSTOMER. ACCORDINGLY, IN NO EVENT SHALL THE COMPANY BE * LIABLE FOR ANY DAMAGES, WHETHER IN CONTRACT OR TORT, INCLUDING ANY * LOST PROFITS OR OTHER INCIDENTAL, CONSEQUENTIAL, EXEMPLARY, OR * PUNITIVE DAMAGES ARISING OUT OF THE USE OR APPLICATION OF THE SPICE * MODEL PROVIDED IN THIS PACKAGE. FURTHER, FAIRCHILD RESERVES THE RIGHT * TO MAKE CHANGES WITHOUT NOTICE TO ANY PRODUCT HEREIN TO IMPROVE, * RELIABILITY, FUNCTION, OR DESIGN. FAIRCHILD DOES NOT CONVEY ANY LICENSE * UNDER PATENT RIGHTS OR ANY OTHER INTELLECTUAL PROPERTY RIGHTS, * INCLUDING THOSE OF THIRD PARTIES. * * FAIRCHILD IS NOT OBLIGATED TO PROVIDE MAINTENANCE OR SUPPORT FOR * THE LICENSED SPICE MODEL. * * ******************************************************************************** * SPECIAL NOTES: ******************************************************************************** * * THE SPICE INPUT FILES CONTAINED ON THIS DISK ARE * BELIEVED TO BE VALID REPRESENTATIONS OF THE INPUT, OUTPUT, I/O AND * ASSOCIATED CIRCUITRY USED ON THE LOGIC DEVICE MODELED. THESE * SPICE SIMULATION INPUT FILES ARE INTENDED TO BE A USEFUL AND * BENEFICIAL TOOL TO THE SYSTEM DESIGNER FOR THE PURPOSE OF MODELING * BUS LOADING AND CERTAIN DRIVE CHARACTERISTICS. HOWEVER, DUE TO THE * COMPLEXITIES INDIGENOUS TO THE MODELING OF TRANSIENT PHENOMENON, * FAIRCHILD SEMICONDUCTOR RECOMMENDS THAT SIMULATED RESULTS BE * SUPPORTED BY LABORATORY CHARACTERIZATION PRIOR TO MAKING FINAL * JUDGMENTS REGARDING DEVICE TRANSIENT PERFORMANCE. FSC STRONGLY * RECOMMENDS THAT SPICE SIMULATION NOT BE USED IN PLACE OF ACTUAL DEVICE * CHARACTERIZATION. * * * ALL MATERIAL CONTAINED ON THIS DISK IS * COPYRIGHT 1998 - FAIRCHILD SEMICONDUCTOR CORPORATION * * * * CONTACT FAIRCHILD AT ATTN: LOGIC APPLICATIONS/SPICE MODELS. * FAIRCHILD SEMICONDUCTOR, M/S 10-26 333 WESTERN AVENUE, S. PORTLAND, * MAINE 04106 OR FAIRCHILD'S TECHNICAL RESPONSE GROUP AT 888-522-5372. * * WWW.FAIRCHILDSEMI.COM * ******************************************************************************** * THIS FILE IS A SUBCIRCUIT SPICE MODEL FOR THE FAIRCHILD SEMICONDUCTOR * LCX FAMILY OF LOGIC DEVICES. IT IS INTENDED FOR USE AS AN INPUT, OUTPUT, * OR I/O * MODEL WHICH WILL ACCURATELY REPRESENT THE OUTPUT CHARACTERISTICS OF * THE FOLLOWING LCX FUNCTIONS: 573 * * THE ACTUAL FUNCTIONALITY OF THIS SUBCIRCUIT I/O MODEL IS A NON-INVERTING * BUFFER. * * THE TERMINALS OF THIS SUBCIRCUIT ARE DESCRIBED AS FOLLOWS: * IN = INPUT TERMINAL * OE = ENABLE TERMINAL * OUT = OUTPUT TERMINAL * GND = GROUND TERMINAL * VCC = POWER SUPPLY TERMINAL * **** FOR FULL PATH INPUT TO OUTPUT USE SUBCIRCUIT CALL: LCXPATH * * SPECIAL NOTES: * 1. THIS SUBCIRCUIT IS NOT INTENDED TO ACCURATELY PREDICT PROPAGA- * TION DELAY TIMES FROM THE INPUT TERMINAL TO THE OUTPUT TERMINAL. * ********************************************************************* * FULL PATH CONNECTION INPUT TO OUTPUT *********************************************************************** .SUBCKT LCX573TM0 IN OUT OE VCC GND X1 IN 5 GND SOIC20MID X2 OUT 9 GND SOIC20MID X3 VCC PWRP GND SOIC20CRNR X4 GND PWRN GND SOIC20CRNR X5 OE 10 GND SOIC20MID X6 24 PWRP 9 10 PWRN LCXOUTTRI X7 5 PWRP 24 PWRN LCXINPUT .ENDS LCX573TM0 ******************************************************************************** * TEST FORCING FUNCTIONS. UNCOMMENT TO TEST SPICE DECK, INCLUDING .END ******************************************************************************** * *VIN1 IN GND PULSE 0.0 3.3 1E-9 2.5E-9 2.5E-9 6.5E-9 20E-9 *VCC1 VCC GND 3.3 *VGND GND PWRN 0 *VOE OE GND 0 * *.TRAN 1.00000E-11 40.00000E-09 START= 0. *.TEMP 25.0000 *.OPTION POST = 2 * *XPKG IN OUT OE VCC GND LCX573TM0 ************************************************************************* * PACKAGE SUBCIRCUITS ************************************************************************** .SUBCKT SOIC20CRNR 1 3 GND R$1 1 2 0.15 R$2 2 3 10000000 L$1 2 4 3.81NH L$2 4 3 1.40NH C$1 3 GND 0.20PF .ENDS .SUBCKT SOIC20MID 1 3 GND R$1 1 2 0.10 R$2 2 3 10000000 L$1 2 4 2.70NH L$2 4 3 1.00NH C$1 3 GND 0.10PF .ENDS ************************************************************************* * NETLIST ************************************************************************* .prot FREELIB Hb4/[GsWFKe78.$2:IXI,8*W>9$4:#8 5[0i]$-$=.3XI,8\WmEu0 >a\u=> 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