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/Title (MC100LVEP14 - 2.5V / 3.3V 1:5 Differential ECL/PECL/HSTL Clock Driver)
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MC100LVEP14 - 2.5V / 3.3V 1:5 Differential ECL/PECL/HSTL Clock Driver
ON Semiconductor
The MC100LVEP14 is a low skew 1−to−5 differential driver, designed
with clock distribution in mind, accepting two clock sources into an input
multiplexer. The ECL/PECL input signals can be either differential or
single−ended (if the VBB output is used). HSTL inputs can be used when
the LVEP14 is operating under PECL conditions.
The LVEP14 specifically guarantees low output−to−output skew.
Optimal design, layout, and processing minimize skew within a device and
from device to device.
To ensure that the tight skew specification is realized, both sides of
any differential output need to be terminated identically into 50
even if only one output is being used. If an output pair is unused, both
outputs may be left open (unterminated) without affecting skew.
The common enable (EN) is synchronous, outputs are enabled/
disabled in the LOW state. This avoids a runt clock pulse when the
device is enabled/disabled as can happen with an asynchronous
control. The internal flip flop is clocked on
2014-04-16T13:50:37-07:00
BroadVision, Inc.
2020-10-12T08:51:41+02:00
2020-10-12T08:51:41+02:00
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