P-Channel Logic Level Enhancement Mode Field Effect Transistor -20V, -1A, 0.41Ω

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Overview

These P-Channel logic level enhancement mode power field effect transistors are produced using ON Semiconductor's proprietary, high cell density, DMOS technology. This very high density process is especially tailored to minimize on-state resistance. These devices are particularly suited for low voltage applications such as notebook computer power management, portable electronics, and other battery powered circuits where fast high-side switching, and low in-line power loss are needed in a very small outline surface mount package.

  • This product is general usage and suitable for many different applications
  • -1 A, -20 V
    RDS(ON) = 0.41Ω @ VGS= -2.7 V
    RDS(ON) = 0.3 Ω @ VGS = -4.5 V
  • Very low level gate drive requirements allowing direct operation in 3V circuits
    VGS(th) < 1.0V
  • Proprietary package design using copper lead frame for superior thermal and electrical capabilities
  • High density cell design for extremely low RDS(ON)
  • Exceptional on-resistance and maximum DC current capability
  • Compact industry standard SOT-23 surface Mount package

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Product

Status

CAD Models

Compliance

Package Type

Case Outline

MSL Type

MSL Temp (°C)

Container Type

Container Qty.

ON Target

V(BR)DSS Min (V)

RDS(on) Max @ VGS = 10 V (mΩ)

Channel Polarity

Configuration

VGS Max (V)

VGS(th) Max (V)

ID Max (A)

PD Max (W)

RDS(on) Max @ VGS = 2.5 V (mΩ)

RDS(on) Max @ VGS = 4.5 V (mΩ)

Qg Typ @ VGS = 4.5 V (nC)

Qg Typ @ VGS = 10 V (nC)

Ciss Typ (pF)

Reference Price

NDS332P

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Active

CAD Model

Pb

A

H

P

SOT-23-3

1

260

REEL

3000

N

-20

-

P-Channel

Single

8

-1

-1

0.5

410

300

2

3.7

195

$0.1393

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