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Product Overview  


For complete documentation, see the data sheet.

Printed On: 7/11/2015

NB3N853501E: Input Mux - 2:1, LVTTL / LVCMOS, 3.3 V, Fanout Buffer - 1:4 LVPECL

Product Description
The NB3N853501E is a low skew 3.3 V supply 2:1:4 clock distribution fanout buffer. An Input MUX selects one of two LVCMOS/LVTTL CLK lines by the CLK_SEL pin (HIGH for CLK1, LOW for CLK0) using LVCMOS/LVTTL levels. A CLK_EN pin can enable or disable the outputs synchronously to eliminate runt pulses using LVCMOS/LVTTL levels (HIGH to enable outputs, LOW to disable output).
Features   Benefits
     
  • Four differential LVPECL Outputs
 
  • Multiple copies of the Clock
  • Operating range: VCC = 3.3 5% V( 3.135 to 3.465 V)
 
  • Ensures operation in the majority of designs
  • Two Selectable LVCMOS/LVTTL CLOCK Inputs
   
  • Up to 266 MHz Clock Operation
   
  • Output to Output Skew: 30 ps
   
  • Device to Device Skew 250 ps (Max.)
   
  • Propagation Delay 1.9 ns (Max.)
   
  • Additive Phase Jitter, RMS: 0.023 ps (Typ)
   
  • Industrial Temp. Range (40C to 85C)
   
Applications   End Products
  • Teleconmmunications
  • Networking
  • Computing Systems
  • SONET/SDH
 
  • LAN/WAN
  • Enterprise Servers
  • ATE
  • Test and Measurement
Selected Electrical Specifications

Product Compliance Status Description Type Channels Input / Output Ratio Input Level Output Level VCC Typ (V) tJitterRMS Typ (ps) tskew(o-o) Max (ps) tpd Typ (ns) tR & tF Max (ps) fmaxClock Typ (MHz) fmaxData Typ (Mbps) Package Type
 Pb-free 
 Halide free 
 Active     Input Mux - 2:1, LVTTL / LVCMOS, 3.3 V, Fanout Buffer - 1:4 LVPECL   Buffer   1   2:1:4 
 LVCMOS 
 LVTTL 
 LVPECL   3.3   0.062   30     700   266     TSSOP-20 
 Pb-free 
 Halide free 
 Active     Input Mux - 2:1, LVTTL / LVCMOS, 3.3 V, Fanout Buffer - 1:4 LVPECL   Buffer   1   2:1:4 
 LVCMOS 
 LVTTL 
 LVPECL   3.3   0.062   30     700   266     TSSOP-20 
Package Availability
Type
PB free
Standard
TSSOP-20 x