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Product Overview  


For complete documentation, see the data sheet.

Printed On: 7/11/2015

NB3N121K: Clock / Data Fanout Buffer, 1:21 Differential, 3.3 V, with HCSL Outputs

Product Description
The NB3N121K is a differential 1:21 Clock and Data fanout buffer with High-speed Current Steering Logic (HCSL) outputs optimized for ultra low propagation delay variation. The NB3N121K is designedwith HCSL PCI Express clock distribution and FBDIMM applications in mind.
Features
 
  • Typical Input Clock Frequency 100, 133, 166, 200, 266, 333 and
    400 MHz
  • 340 ps Typical Rise and Fall Times
  • 800 ps Typical Propagation Delay
  • 100 ps Max Within Device Skew
  • 150 ps Max DevicetoDevice Skew
  • Delta-tpd 100 ps Maximum Propagation Delay Variation Per Each Differential Pair
  • 0.1 ps Typical RMS Additive Phase Jitter
  • LVDS Output Levels Optional with Interface Termination
  • Operating Range: VCC = 3.0 V to 3.6 V with GND = 0 V
  • Typical HCSL Output Level (700 mV PeaktoPeak)
Applications   End Products
  • Clock Distribution
  • PCIe I, II, III
  • Networking
  • High End Computing
  • Routers
 
  • Servers
Selected Electrical Specifications

Product Compliance Status Description Type Channels Input / Output Ratio Input Level Output Level VCC Typ (V) tJitterRMS Typ (ps) tskew(o-o) Max (ps) tpd Typ (ns) tR & tF Max (ps) fmaxClock Typ (MHz) fmaxData Typ (Mbps) Package Type
 Pb-free 
 Halide free 
 Active     Clock / Data Fanout Buffer, 1:21 Differential, 3.3 V, with HCSL Outputs   Buffer   1   1:21 
 CMOS 
 ECL 
 HCSL 
 LVDS 
 TTL 
 HCSL   3.3   0.1   100   0.8   700   400     QFN-52 
 Pb-free 
 Halide free 
 Active     Clock / Data Fanout Buffer, 1:21 Differential, 3.3 V, with HCSL Outputs   Buffer   1   1:21 
 CMOS 
 ECL 
 HCSL 
 LVDS 
 TTL 
 HCSL   3.3   0.1   100   0.8   700   400     QFN-52 
Package Availability
Type
PB free
Standard
QFN-52 x