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Product Overview  


For complete documentation, see the data sheet.

Printed On: 7/11/2015

NB3N108K: Clock / Data Fanout Buffer, 1:8 Differential, 3.3 V, with HCSL Outputs

Product Description
The NB3N108K is a differential 1:8 Clock and Data fanout buffer with High-speed Current Steering Logic (HCSL) outputs optimized for ultra low propagation delay variation. The NB3N108K is designed with HCSL clock distribution and FBDIMM applications in mind.
Features   Benefits
     
  • 0.1 ps Typical RMS Phase Jitter
 
  • Best in class for jitter performance
  • Typical Input Clock Frequency 100, 133, 166, or 400 MHz
   
  • 220 ps Typical Rise and Fall Times
   
  • 800 ps Typical Propagation Delay
   
  • tpd 100 ps Maximum Propagation Delay 100 ps Delta tpd Variation Per Each Diff Pair
   
  • Operating Range: VCC = 3.0 V to 3.6 V with VEE = 0 V
   
  • Differential HCSL Output Levels or LVDS Output Levels with Interface Termination
   
Applications   End Products
  • Clock distribution
  • PCIe I, II, II
  • Networking and Communications
  • High End Computing
  • Routers
 
  • Servers
  • FBDIMM Memory Card
  • Ethernet Switch/Routers
Selected Electrical Specifications

Product Compliance Status Description Type Channels Input / Output Ratio Input Level Output Level VCC Typ (V) tJitterRMS Typ (ps) tskew(o-o) Max (ps) tpd Typ (ns) tR & tF Max (ps) fmaxClock Typ (MHz) fmaxData Typ (Mbps) Package Type
 Pb-free 
 Halide free 
 Active     Clock / Data Fanout Buffer, 1:8 Differential, 3.3 V, with HCSL Outputs   Buffer   1   1:8 
 CMOS 
 ECL 
 HCSL 
 LVDS 
 TTL 
 HCSL   3.3   0.1   100   0.8   400   400   400   QFN-32 
 Pb-free 
 Halide free 
 Active     Clock / Data Fanout Buffer, 1:8 Differential, 3.3 V, with HCSL Outputs   Buffer   1   1:8 
 CMOS 
 ECL 
 HCSL 
 LVDS 
 TTL 
 HCSL   3.3   0.1   100   0.8   400   400   400   QFN-32 
Package Availability
Type
PB free
Standard
QFN-32 x