2.5 V / 3.3 V 1:4 Differential Input to LVDS Fanout Buffer / Translator

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Overview

The NB3L8504S is a differential 1:4 LVDS fanout buffer/translator with OE control for each differential output. The differential inputs which can be driven by either a differential or single−ended input, can accept various logic level standards such asLVPECL, LVDS, HSTL, HCSL and SSTL. These signals are then translated to four identical LVDS copies of the input up to 700 MHz. As such, the NB3L8504S is ideal for Clock distribution applications that require low skew.

  • Telecom
  • Ethernet
  • Networking
  • SONET
  • Routers
  • Switches
  • Four Differential LVDS Outputs
  • Each Differential Output has OE Control
  • 700 MHz Maximum Output Frequency
  • 660 ps Max Output Rise and Fall Times, LVCMOS
  • Translates Differential Input to LVDS Levels
  • Additive Phase Jitter RMS: < 100 fs Typical
  • 50 ps Maximum Output Skew
  • 350 ps Maximum Part−to−part Skew
  • 1.3 ns Maximum Propagation Delay
  • Operating Range: VCC = 2.375 V to 3.630 V
  • −40°C to +85°C Ambient Operating Temperature

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Type

Channels

Input / Output Ratio

Input Level

Output Level

VCC Typ (V)

tJitterRMS Typ (ps)

tskew(o-o) Max (ps)

tpd Typ (ns)

tR & tF Max (ps)

fmaxClock Typ (MHz)

fmaxData Typ (Mbps)

Reference Price

NB3L8504SDTG

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Active

CAD Model

Pb

A

H

P

TSSOP-16

1

260

TUBE

96

Y

Buffer

1

1:4

SSTL

LVDS

3.3

0.07

50

1.3

660

700

-

Price N/A

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NB3L8504SDTR2G

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Active

CAD Model

Pb

A

H

P

TSSOP-16

1

260

REEL

2500

Y

Buffer

1

1:4

SSTL

LVDS

3.3

0.07

50

1.3

660

700

-

Price N/A

More Details

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