The NB2308A is a versatile, 3.3V zero delay buffer designed to distribute high-speed clocks. It is available in a 16-pin package. The part has an on-chip PLL which locks to an input clock presented on the REF pin. The PLL feedback is required to be driven to FBK pin, and can be obtained from one of the outputs. The input-to-output propagation delay is guaranteed to be less than 250ps, and the output-to-output skew is guaranteed to be less than 200ps. The NB2308A has two banks of four outputs each, which can be controlled by the select inputs as shown in the Select Input Decoding Table. If all the output clocks are not required, Bank B can be three-stated. The select input also allows the input clock to be directly applied to the outputs for chip and system testing purposes. Multiple NB2308A devices can accept the same input clock and distribute it. In this case the skew between the outputs of the two devices is guaranteed to be less than 700ps. The NB2308A is available in five different configurations (Refer to NB2308A Configurations Table). The NB2308AI1 is the base part, where the output frequencies equal the reference if there is no counter in the feedback path. The NB2308AI1H is the high-drive version of the -1 and the rise and fall times on this device are much faster. The NB2308AI2 allows the user to obtain 2X and 1X frequencies on each output bank. The exact configuration and output frequencies depends on which output drives the feedback pin. The NB2308AI3 allows the user to obtain 4X and 2X frequencies on the outputs. The NB2308AI4 enables the user to obtain 2X clocks on all outputs. Thus, the part is extremely versatile, and can be used in a variety of applications. The NB2308AI5H is a high-drive version with REF/2 on both banks.
Zero Input - Output Propagation Delay, Adjustable by Capacitive Load on FBK Input
Multiple Configurations - Refer to NB2308A Configurations Table
Input Frequency Range: 15 MHz to 133 MHz
Multiple Low-Skew Outputs
Output-Output Skew Less than 200 ps
Device-Device Skew Less than 700 ps
Two banks of four outputs, three-stateable by two select inputs
Less than 200 ps Cycle-to-Cycle Jitter (-1, -1H, -4, -5H)
Available in 16-pin SOIC and TSSOP Packages
Advanced 0.35 µ CMOS Technology
High-Speed clock distribution in PC, workstation, datacom, and telecom applications.