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MC100EP29: ECL Dual Differential Clock/Data D Flip-Flop With Set and Reset

Overview
Specifications
Packages
Datasheet: 3.3V / 5V ECL Dual Differential Data and Clock D Flip-Flop With Set and Reset
Rev. 9 (105kB)
»View Reliability Data
»View Material Composition
»Product Change Notification (10)
Product Overview
Product Description
The MC10/100EP29 is a dual master-slave flip flop. The device features fully differential Data and Clock inputs as well as outputs. The MC10/100EP29 is functionally equivalent to the MC10/100EL29. Data enters the master latch when the clock is LOW and transfers to the slave upon a positive transition on the clock input.

The differential inputs have special circuitry which ensures device stability under open input conditions. When both differential inputs are left open the Dbar input will pull down to VEE and the Dbar input will bias around VCC/2. The outputs will go to a defined state, however the state will be random based on how the flip flop powers up.

Both flip flops feature asynchronous, overriding Set and Reset inputs. Note that the Set and Reset inputs cannot both be HIGH simultaneously.

The VBB pin, an internally generated voltage supply, is available to this device only. For single-ended input conditions, the unused differential input is connected to VBB as a switching reference voltage. VBB may also rebias AC coupled inputs. When used, decouple VBB and VCC via a 0.01uF capacitor and limit current sourcing or sinking to 0.5 mA. When not used, VBB should be left open.

The 100 Series Contains Temperature Compensation
Features
 
  • Maximum Frequency > 3 GHz Typical
  • 500 ps Typical Propagation Delays
  • PECL Mode Operating Range: VCC = 3.0 V to 5.5 V with VEE = 0 V
  • NECL Mode Operating Range: VCC = 0 V with VEE = -3.0 V to -5.5 V
  • Open Input Default State
  • Safety Clamp on Inputs
  • These are Pb−Free Devices
Applications
  • Functionally equivalent to the MC10/100EL29
Technical Documentation & Design Resources
Application Notes (14) Package Drawings (2)
Simulation Models (2) Evaluation Board Documents (1)
Data Sheets (1)  
Evaluation/Development Tool Information
Product Status Compliance Short Description Action
ECLTSSOP20EVB Active
High Frequency TSSOP20 Evaluation Board
Avnet (2015-07-09) : 2
Digikey (2015-07-09) : 1
Availability and Samples
Product
Status
Compliance
Description
Package
MSL*
Container
Budgetary Price/Unit
Type
Case Outline
Type
Qty.
MC100EP29DT Last Shipments
Pb-free
ECL Dual Differential Clock/Data D Flip-Flop With Set and Reset TSSOP-20 948E-02 1 Tube 75  
MC100EP29DTG Active
Pb-free
Halide free
ECL Dual Differential Clock/Data D Flip-Flop With Set and Reset TSSOP-20 948E-02 1 Tube 75 Contact Sales Office
MC100EP29DTR2 Last Shipments
Pb-free
ECL Dual Differential Clock/Data D Flip-Flop With Set and Reset TSSOP-20 948E-02 1 Tape and Reel 2500  
MC100EP29DTR2G Active
Pb-free
Halide free
ECL Dual Differential Clock/Data D Flip-Flop With Set and Reset TSSOP-20 948E-02 1 Tape and Reel 2500 Contact Sales Office
MC100EP29MNG Active
Pb-free
Halide free
ECL Dual Differential Clock/Data D Flip-Flop With Set and Reset QFN-20 485E-01 1 Tube 92 Contact Sales Office
MC100EP29MNTXG Active
Pb-free
Halide free
ECL Dual Differential Clock/Data D Flip-Flop With Set and Reset QFN-20 485E-01 1 Tape and Reel 3000 Contact Sales Office
Moisture Sensitivity level (MSL) for surface mount devices (lead free measured at 260°C reflow, non lead free at 235°C reflow)
Market Leadtime (weeks) : Contact Factory
Market Leadtime (weeks) : 2 to 4
Arrow   (Fri Jul 10 18:27:45 MST 2015) : 308
Avnet   (2015-07-09) : <100
Digikey   (2015-07-09) : <1K
FutureElectronics   (2015-07-09) : <1K
Mouser   (2015-07-09) : <100
ON Semiconductor   (2015-07-08) : 4,200
PandS   (2015-07-09) : <100
Market Leadtime (weeks) : Contact Factory
Market Leadtime (weeks) : 8 to 12
Market Leadtime (weeks) : 2 to 4
Arrow   (Fri Jul 10 18:27:58 MST 2015) : 40
Mouser   (2015-07-09) : <100
ON Semiconductor   (2015-07-08) : 4,784
PandS   (2015-07-09) : <100
Market Leadtime (weeks) : 8 to 12
ON Semiconductor   (2015-07-08) : 3,000
Datasheet: 3.3V / 5V ECL Dual Differential Data and Clock D Flip-Flop With Set and Reset
Rev. 9 (105kB)
»View Reliability Data
»View Material Composition
»Product Change Notification (10)
Product Overview

Product Compliance Status Description Type Bits Input Level Output Level VCC Typ (V) tJitter Typ (ps) tpd Typ (ns) tsu Min (ns) th Min (ns) trec Typ (ns) tR & tF Max (ps) fToggle Typ (MHz) Package Type
 Pb-free 
 Halide free 
 Active     ECL Dual Differential Clock/Data D Flip-Flop With Set and Reset   D-Type   2 
 CML 
 ECL 
 ECL 
 3.3 
 5 
 0.2   0.42   0.1   0.1   0.08   250   3000   TSSOP-20 
 Pb-free 
 Halide free 
 Active     ECL Dual Differential Clock/Data D Flip-Flop With Set and Reset   D-Type   2 
 CML 
 ECL 
 ECL 
 3.3 
 5 
 0.2   0.42   0.1   0.1   0.08   250   3000   TSSOP-20 
 Pb-free 
 Halide free 
 Active     ECL Dual Differential Clock/Data D Flip-Flop With Set and Reset   D-Type   2 
 CML 
 ECL 
 ECL 
 3.3 
 5 
 0.2   0.42   0.1   0.1   0.08   250   3000   QFN-20 
 Pb-free 
 Halide free 
 Active     ECL Dual Differential Clock/Data D Flip-Flop With Set and Reset   D-Type   2 
 CML 
 ECL 
 ECL 
 3.3 
 5 
 0.2   0.42   0.1   0.1   0.08   250   3000   QFN-20 
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