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SP110: 0.11 µm Standard Cell ASIC

Overview
Product Description
The ON Semiconductor SP110 standard cell family combines high density logic and memory with extensive I/O capabilities and advanced off-chip memory interfaces. The SP110 family offers small die sizes for low cost, medium to high volume applications.

Features
  • Minimum drawn length: 115 nm, 110 nm Leff
  • Up to 20 M logic gates and 20 M bits of RAM
  • Excellent performance:
    • 450 MHz for a zero-stage 18 x 18 multiplier
    • 2.2 ns delay for a 512 x 36 DPRAM
    • 1.2 V core operation
    • 1.2 V, 1.5 V, 1.8 V, 2.5 V, 3.3 V and 5 V tolerant I/O cells
    • 3.3 V tolerance on 1.8 V and 2.5 V I/O cells
    • 5 V tolerance on 3.3V I/O cells
  • Power dissipation: 9.0 nW/MHz/gate (FO=1; VDD=1.2 V)
  • Junction temperature range: -40°C to 125°C
  • Cost driven architecture:
    • Up to 9 levels of metal (including RDLs) provides lowest device cost
    • Wire-bond packaging for small to medium I/O count devices
    • Flip-chip packaging for larger I/O count devices or for high performance applications
  • Extensive library for quick design:
    • Extensive Foundation IP digital design kit (DDK) available
      • I/O, memory compilers and timing generators
      • High Performance Core Library
      • High Density Core Library
      • Low Power Core Library
      • Low Leakage Core Library
    • System IP blocks include SerDes, uProcessors, Memory Interfaces and USB 2.0
  • Extensive I/O cell options:
    • LVTTL, LVCMOS, PCI, PCIX-66/100/133 (3.3 V or 5 V Tolerant), SSTL Class I/II (1.5 V, 1.8 V, 2.5 V), HSTL Class I/II (1.5 V), LVPECL, LVDS, DCI, CML
    • 25 Ω to 75 Ω output impedance for single ended
    • 50 Ω or 75 Ω single ended or 100 Ω or 150 Ω differential
    • Standard and slew rate limited output drivers
  • Extensive memory support:
    • Synchronous single, 2-port and dual port up to 16 K x 128
    • Dedicated BIST ports
    • Memory compilers optimized for speed or density
    • Memory performance to 450 MHz for a 2048 x 32 configuration
    • Programmable ROM available
  • FPGA conversion specific memory features:
    • Output register mode, shift register mode, FIFO mode
    • Xilinx read before write
    • Xilinx no change mode
    • Altera MRAM size
  • Integrated timing generator and frequency synthesis:
    • Suite of general purpose PLLs
    • VCO range of 50 MHz to 1 GHz
  • High speed SerDes up to 4 Gbps per channel:
    • 10G Ethernet
      • 4 Channel XAUI PHY, each lane running at 3.125 Gbps, with an aggregate data through-put of 10 Gbps
      • PCS and MAC layers available
    • EPON
      • PHY available, PMA level compliance
    • Gigabit Ethernet at 1.25 Gbps
      • PHY, PCS and MAC layers available
    • PCI-Express Gen 1 at 2.5 Gbps
      • 1x, 4x, or 8x Lane Configurations with PIPE interface
      • Link and Transaction layers available
    • SATA2
      • 3 Gbps 1 lane PHY and controller
    • Serial Rapid I/O (SRIO) at 2.5 Gbps
      • 1x, 4x lane configurations
    • General Purpose up to 4 Gbps
    • Supports an extensive library of soft IP including Ethernet functions, microprocessors and peripherals, interface controllers, and others
  • High speed parallel interfaces:
    • DDR2 at 667 Mbps
    • High Speed LVDS Interfaces up to 1.0 Gbps
  • USB 2.0
    • High/Full Speed Multi-Point OTG Controller
    • High Speed UTMI+ Transceiver w/ charge pump
    • Support for Software Stack
  • Extensive packaging capabilities:
    • 0. 65 mm to 1.27 mm pitch BGAs
    • CSPs, QFPs, CQFPs, TQFPs, PLCCs, LCCs, JLCCs
    • Differential pair matching
    • Controlled impedance traces
    • Stacked packages with flash
    • Burn-in capability as required
  • Extensive DFT methodology:
    • Scan-chain insertion and reordering
    • Built-in self test (BIST) for memory blocks
    • Automatic test program generation (ATPG)
    • JTAG boundary scan insertion
  • ESD protection 2,000 V HBM, 500 V CDM, 200 V MM
  • Latchup >200 mA @ 125°C
  • MLR (Multi Layer Reticles) available

Phase 2

  • Extended Military / Aerospace Application Support
    • Extended Temperature Qualification
    • QML Qualification
  • Hardened ARM926EJS Core with Sub-System
  • Expanded Parallel Interfaces
    • DDR2 800 MHz
  • Non-Volatile Memory
    • One Time Programmable (OTP) Bit Array
  • High Performance Clock Circuitry
    • Ultra Low Jitter PLL
    • High Performance Digital Locked Loop (DLL)
  • Analog functions including ADCs and DACs
Applications

SP110 targets low to high volume digital ASIC products in the Military and Aerospace, Industrial, Networking & Telecommunications, Computing and Consumer markets. The high performance capabilities of the process make SP110 ideal for high speed applications, including those requiring external high performance memory interfaces, PCI-Express, 10 Gigabit Ethernet, and Gigabit Ethernet SerDes. Combined with support for a rich family of IP, SP110 supports applications in military munitions, radar systems, avionics, secure communications, wireless infrastructure, industrial controls, printers and infotainment. The ON Semiconductor RTL signoff and netlist hand-off flows provide quick and seamless access for SP110 designs.

Unique 110 nm Process Architecture
The ON Semiconductor SP110 standard cell platform meets the performance and cost goals of many applications while avoiding high development cost and potential process "overkill" associated with more advanced technologies. The SP110 process is designed with 110 nm Leff gate length resulting in better performance than TSMC's 130 nm (G process) while maintaining low power consumption. The dense standard cell architecture allows for competitive piece part pricing with much lower tooling costs than TSMC's 130 nm tooling cost and significantly lower than a 90 nm technology.

SP110 wafers may be produced at either ON Semiconductor's U.S. wafer fab, or at TSMC. This dual source capability provides a flexible on-shore manufacturing path critical to the military market as well as local support for Asian test and packaging houses depending on customer needs.

The SP110 platform includes a comprehensive suite of System IP optimized for the 110 nm manufacturing process which allows for a high level of system integration for a variety of applications.

SP110 provides a cost effective solution for applications with gate counts up to 20 million and up to 20 million bits of memory.

Targeted Quality Standards
With domestic manufacturing that includes ITAR, QML, and DO-254 support, SP110 meets the specific quality standards needed to support military and aerospace applications.

Second Source for Existing Products
The ASIC-to-ASIC conversion capability from ON Semiconductor allows SP110 to be a cost-effective alternative supply for existing high-volume products.

FPGA Prototype Designs
Based on the extensive experience of ON Semiconductor with FPGA conversions, ASIC designs prototyped in FPGAs, or those which are partially prototyped or partitioned between FPGAs and other devices such as DDR2/3/QDR or SerDes interfaces, can be integrated into a single SP110 device.

ON Semiconductor can also provide customers with a comprehensive library of soft IP that can be prototyped in an FPGA further easing the process of getting to a cost competitive, low power ASIC for production.

FPGA Conversion
The SP110 product roadmap will be expanded to offer support for 1.2 V FPGA devices, including:

  • Full I/O
  • Memory feature compatibility
  • DLL/PLL equivalence.

ASIC Design Tools and Methodology

ON Semiconductor ASICs are supported on leading third-party software platforms:

  • Cadence®
  • Synopsys®
  • Mentor Graphics™

The ON Semiconductor design flow integrates leading third-party design tools with ON Semiconductor proprietary tools to offer a flexible design interface for mid-range ASIC designs with RTL sign-off, ASIC netlists for ASIC-to-ASIC conversion and FPGA designs for FPGA-to-ASIC conversion. The ON Semiconductor methodology ensures a tight, well-coupled flow from design to production. The dedicated, experienced engineering staff from ON Semiconductor can assist at any step of the design process.